View S29GL256S_9002067.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-98285 rev. * o revised september 21, 2017 s29gl01gs/s29gl512s S29GL256S/s29gl128s 1-gbit (128 mbyte)/5 12-mbit (64 mbyte)/ 256-mbit (32 mbyte)/ 128-mbit (16 mbyte), 3.0 v, gl-s flash memory general description the cypress ? s29gl01g/512/256/128s are mirrorbit ? eclipse flash products fabricated on 65 nm process technology. these devices offer a fast page access time as fast as 15 ns with a co rresponding random access time as f ast as 90 ns. they feature a write buffer that allows a maxim um of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. this mak es these devices ideal for todays embedded applications that require higher density, better pe rformance and low er power cons umption. distinctive characteristics ? cmos 3.0 volt core with versatile i/o ? 65 nm mirrorbit eclipse technology ? single supply (v cc ) for read / program / e rase (2.7v to 3.6v) ? versatile i/o feature C wide i/o voltage range (v io ): 1.65v to v cc ? x16 data bus ? asynchronous 32-byte page read ? 512-byte programming buffer C programming in page multipl es, up to a maximum of 512 bytes ? single word and multiple p rogram on same word options ? automatic error checking and correction (ecc) C internal hardware ecc with single bit error correction ? sector erase C uniform 128-kbyte sectors ? suspend and resume command s for program and erase operations ? status register, data polling, and ready/busy pin methods to determine device status ? advanced sector protection (asp) C volatile and non-volatile pro tection methods for each sector ? separate 1024-byte one time program (otp) array with two lockable regions ? common flash interface (cfi) parameter table ? temperature range / grade C industrial (-40c to +85c) C industrial plus(-40c to +105c) C automotive, aec-q100 grade 3 (-40 c to +85 c) C automotive, aec-q100 grade 2 (-40 c to +105 c) ? 100,000 program / erase cycles ? 20 years data retention ? packaging options C 56-pin tsop C 64-ball laa fortifi ed bga, 13 mm x 11 mm C 64-ball lae fortifi ed bga, 9 mm x 9 mm C 56-ball vbu fortified bga, 9 mm x 7 mm
document number: 001-98285 rev. *o page 3 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s performance summary maximum read access times density voltage range random access time (t acc ) page access time (t pacc ) ce# access time (t ce ) oe# access time (t oe ) 128 mb full v cc = v io 90 15 90 25 versatileio v io 1002510035 256 mb full v cc = v io 90 15 90 25 versatileio v io 1002510035 512 mb full v cc = v io 1001510025 versatileio v io 1102511035 1 gb full v cc = v io 1001510025 versatileio v io 1102511035 typical program and erase rates buffer programming (512 bytes) 1.5 mb/s sector erase (128 kbytes) 477 kb/s maximum curren t consumption active read at 5 mhz, 30 pf 60 ma program 100 ma erase 100 ma standby 100 a
document number: 001-98285 rev. *o page 3 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s contents general description ............................................................. 2 distinctive characteristics .................................................. 2 performance summary ........................................................ 3 1. product overview ........................................................ 4 2. address space maps ................................................... 6 2.1 flash memory array.......................................... ............. 7 2.2 device id and cfi (id-cfi) aso .............................. ..... 8 2.3 device id and common flash interface (id-cfi) aso map automotive only ........... ................................... .......... 9 2.4 status register aso......................................... ........... 10 2.5 data polling status aso... .............. ........... ......... ......... 10 2.6 secure silicon region aso ................................... ...... 10 2.7 sector protection control................................... .......... 11 2.8 ecc status aso.............................................. ............ 11 3. data protection .......................................................... 13 3.1 device protection methods ................................... ....... 13 3.2 command protection .......................................... ......... 13 3.3 secure silicon region (otp)................................. ...... 13 3.4 sector protection methods .............. ........... .......... ........ 14 4. read operations ........................................................ 19 4.1 asynchronous read........................................... .......... 19 4.2 page mode read .............................................. ........... 19 5. embedded operations ............................................... 20 5.1 embedded algorithm controll er (eac) ......... ........ ....... 20 5.2 program and erase summary ................................... .. 21 5.3 automatic ecc ............................................... ............. 22 5.4 command set ................................................. ............. 23 5.5 status monitoring ........ ................................... .............. 34 5.6 error types and clearing procedures ......................... 40 5.7 embedded algorithm perform ance table..... ............... 43 6. data integrity .............................................................. 54 6.1 erase endurance ............................................. ............ 54 6.2 data retention .............................................. ............... 54 7. software interface reference ................................... 55 7.1 command summary ............................................. ....... 55 7.2 device id and common fl ash interface (id-cfi) aso map ........................................................ ............. 58 7.3 device id and common fl ash interface (id-cfi) aso map ........................................................ ............. 63 8. signal descriptions ................................................... 64 8.1 address and data configuration.............................. .... 64 8.2 input/output summary........................................ ......... 64 8.3 versatile i/o feature....................................... ............. 65 8.4 ready/busy# (ry/by#) ........................................ ....... 65 8.5 hardware reset .............................................. ............. 65 9. signal protocols ......................................................... 66 9.1 interface states............................................ ................ 66 9.2 power-off with hardware data protection ................... 6 6 9.3 power conservation modes.................................... ..... 67 9.4 read ........................................................ ..................... 67 9.5 write ....................................................... ...................... 68 10. electrical specifications ............................................. 69 10.1 absolute maximum ratings ................................... ....... 69 10.2 latchup characteristics . ............ ............ ........... ............ 69 10.3 thermal resistance ......................................... ............. 69 10.4 operating ranges........................................... .............. 69 10.5 dc characteristics ......................................... ............... 72 10.6 capacitance characterist ics ............... ........ ......... ......... 74 11. timing specifications ................................................. 75 11.1 key to switching wavefo rms ................................. ....... 75 11.2 ac test conditions ......................................... .............. 75 11.3 power-on re set (por) and warm reset .................... 76 11.4 ac characteristics ......................................... ............... 78 12. physical interface ....................................................... 90 12.1 56-pin tsop................................................ ................. 90 12.2 64-ball fbga ............................................... ................. 92 12.3 56-ball fbga ............................................... ................. 95 13. special handling instructions for fbga package ... 96 14. ordering information .................................................. 97 15. other resources ....................................................... 102 15.1 cypress flash memory roa dmap .............................. 102 15.2 links to software .......................................... .............. 102 15.3 links to application note s................................. .......... 102 16. revision history ........................................................ 103
document number: 001-98285 rev. *o page 4 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 1. product overview the gl-s family consists of 128-m bit to 1gbit, 3.0v core, versa tile i/o, non-volatile, flash me mory devices. these devices hav e a 16-bit (word) wide data bus and use only word boundary addresse s. all read accesses provide 16 bits of data on each bus transf er cycle. all writes take 16 bits of data from each bus transfer c ycle. figure 1.1 block diagram : note: ** a max gl01gs = a25, a max gl512s = a24, a max gl256s = a23, a max gl128s = a22 the gl-s family combines the bes t features of exe cute in place (xip) and data storage flash memo ries. this family has the fast random access of xip f lash along with the high density and fast program speed of dat a storage flash. read access to any random location takes 90 ns to 120 ns depending on device density and i/o power supply voltage. ea ch random (initial) access reads an entire 32-byte aligned group of data called a page. other wor ds within the same p age may be read by changing only the low order 4 bit s of word address. each access within the same page takes 15 n s to 30 ns. this is called page mode read. changing any of the hi gher word address bits will se lect a different page and begin a new initial access. all read accesses are asynchronous. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp# ce# oe# stb stb dq15 ? dq0 sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0
document number: 001-98285 rev. *o page 5 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s the device control logic is su bdivided into two parallel operat ing sections, the host interface controller (hic) and the embed ded algorithm controller (eac). hic monitors signal levels on the d evice inputs and drives outputs as needed to complete read and write data transfers with the host system. hic delivers data from the currently entered add ress map on read trans fers places write transfer address and data informati on into the eac command memo ry notifies the eac of power t ransition, hardware reset, and write transfers. the eac looks in the command memory, after a w rite transfer, for legal comm and sequences and performs the related embedded algorithms. changing the non-volatile data in the memory array requires a c omplex sequence of operations that are called embedded algorithms (ea). the algorithm s are managed ent irely by the dev ice internal eac. the main algorithms perform programming and erase of the main arr ay data. t he host system writes command co des to the flash device addre ss space. the eac receives the commands, performs all the necessa ry steps to complete the comm and, and provides sta tus information durin g the progress of an ea. the erased state of each memory bit is a logic 1. programming c hanges a logic 1 (high) to a logic 0 (low). only an erase opera tion is able to change a 0 t o a 1. an erase oper ation must be perfor med on an entire 128-kbyte alig ned and length gro up of data cal l a sector. when shipped from cyp ress all sectors are erased. programming is done via a 512-byte write buffer. it is possible to write from 1 to 256 words, anywhere within the write buffer before starting a programming operation. within the flash memory array , each 512-byte aligned group of 512 bytes is cal led a line. a programming operation transfers v olatile data fr om the write bu ffer to a non-volatile memory array line. the operation is call ed write buffer programming. as the device transfers each 32- byte aligned page of data that was loaded into the wr ite buffer to the 512-byte flash array li ne, internal logic programs an ecc co de for the page into a portion of the memory array not visible to the host system software. t he internal logic checks the ecc information during the initial ac cess of every array read operat ion. if needed, the ecc informat ion corrects a one bit e rror during the initial access time. the write buffer is filled with 1s after reset or the completi on of any operation using the write buffer. any locations not w ritten to a 0 by a write to buffer command are by default still filled with 1 s. any 1s in the write buffer do not affect data in the memor y array during a programming operation. as each page of data that was l oaded into the write buffer is t ransferred to a memory array line. sectors may be individually prote cted from program and erase op erations by the advanced sector protection (asp) feature set. asp provides several, hardware a nd software controlled, volatil e and non-volatile, methods to sel ect which sectors are protect ed from program and erase operations. table 1.1 s29gl-s address map type count addresses address within page 16 a3 - a0 address within write buffer 256 a7 - a0 page 4096 a15 - a4 write-buffer-line 256 a15 - a8 sector 1024 (1 gb) 512 (512 mb) 256 (256 mb) 128 (128 mb) a max - a16
document number: 001-98285 rev. *o page 6 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s software interface 2. address space maps there are several separate addr ess spaces that m ay appear withi n the address range of the flas h memory device. one address space is visible (entered) at any given time. ? flash memory array: th e main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations. ? id/cfi: a memory arra y used for cypress factory programmed devi ce characteristics informati on. this area contains the device identification (id) and common flash interface (cfi) inf ormation tables. ? secure silicon region (ssr): a o ne time programmable (otp) non- volatile memory array us ed for cypress factory programmed permanent data, and cu stomer programmable permanent data. ? lock register: an otp non-volatil e word used to configure the a sp features and lock the ssr. ? persistent protection bits (ppb) : a non-volatile f lash memory a rray with one bit for each sector. when programmed, each bit protects the rel ated sector from eras ure and programming. ? ppb lock: a volatile register bit u sed to enable or disable pro gramming and erasure of the ppb bits. ? password: an otp non-volatile a rray used to store a 64-bit pass word used to enable changi ng the state of the ppb lock bit when using password mode sector protection. ? dynamic protection bits (dyb): a volatile array with one bit fo r each sector. when set, each bi t protects the related sector from erasure and programming. ? status register: a volatile regi ster used to display embedded a lgorithm status. ? data polling status: a volatile r egister used as an alternate, legacy software compatible, way to display embedded algorithm status. ? ecc status: provides the status o f any error detection or corre ction action taken when r eading the selected page. the main flash memory array is the primary and d efault address space but, it may be overlaid by one other address space, at an y one time. each alternate address space is called an address spa ce overlay (aso). each aso replaces (o verlays) the entire flash device address ra nge. any address range not defined by a part icular aso address map, is reserved for future use. all read accesses outside of a n aso address map returns non-va lid (undefined) data. the locat ions will display actively driven data but the meaning of whatever 1 s or 0s appear are not defined. there are four device operating modes that determine what appea rs in the flash device addres s space at any given time: ? read mode ? data polling mode ? status register (sr) mode ? address space overlay (aso) mode in read mode the entir e flash memory array may be directly read by the host system memory con troller. the memory device embedded algorithm controller (eac ), puts the device in read mo de during power-on, after a hard ware reset, aft er a command reset, or after an embedded alg orithm (ea) is suspended. read a ccesses and command writes a re accepted in read mode. a subset of commands are accepted i n read mode when an ea is susp ended. while in any mode, the status re gister read command may be issu ed to cause the status registe r aso to appear at every word address in the device address spac e. in this status register as o mode, the device interface w aits for a read access and, any w rite access is ignored. the next re ad access to the device accesses the content of the status regist er, exits the status register a so, and returns to the previous (ca lling) mode in which the status register read command was received. in ea mode the eac is performing an embedded algorithm, such as programming or erasing a non-vo latile memory array. while in ea mode, none of the main flash m emory array is readable becaus e the entire flash device addre ss space is replaced by the data polling status aso. data pollin g status will appe ar at every wo rd location in the de vice address space.
document number: 001-98285 rev. *o page 7 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s while in ea mode, only a program / erase suspend command or the status register read comma nd will be accept ed. all other commands are ignored. thus, no ot her aso may be entered from th e ea mode. when an embedded algorithm is suspended, the data polling aso i s visible until the device has suspended the ea. when the ea is suspended the data polling as o is exited and flash array dat a is available. the data po lling aso is reentered when the suspended ea is resumed, until the ea is again suspended or fin ished. when an embedded algorit hm is completed, the data polling aso is exited and the de vice goes to the previous (call ing) mode (from which the emb edded algorithm was started). in aso mode, one of the remaini ng overlay address spaces is ent ered (overlaid on the main flash array address map). only one aso may be enter ed at any one time. comman ds to the device affe ct the currently entered aso. onl y certain commands are valid for each aso. these are listed in the table 7.1 on page 55 , in each aso related section of the table. the following asos have non-volat ile data that may be programme d to change 1s to 0s: ? secure silicon region ? lock register ? persistent protection bits (ppb) ? password ? only the ppb aso has non-volatil e data that may be erased to ch ange 0s to 1s when a program or erase command is issued while one of the non- volatile asos is entered, the ea operates on the aso. the aso is not readable while the ea is a ctive. when the ea is complete d the aso remains ent ered and is again r eadable. suspend and resume commands are ignored duri ng an ea operating on any of th ese asos. 2.1 flash memory array the s29gl-s family has uniform sector architecture with a secto r size of 128 kb. table 2.1 to table 2.4 shows the sector architecture of the four devices. table 2.1 s29gl01gs sector and memory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 1024 sa00 0000000h-000ffffh sector starting address ::C sa1023 3ff0000h-3ffffffh sector ending address table 2.2 s29gl512s sector and m emory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 512 sa00 0000000h-000ffffh sector starting address ::C sa511 1ff0000h-1ffffffh sector ending address table 2.3 S29GL256S sector and m emory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 256 sa00 0000000h-000ffffh sector starting address ::C sa255 0ff0000h-0ffffffh sector ending address
document number: 001-98285 rev. *o page 8 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: these tables have been condensed to show sector related inform ation for an entire device on a single page sectors and their address ranges that are not exp licitly listed (such as sa001-sa 510) have sectors starting and ending addresses that form the s ame pattern as all other sectors o f that size. for example, all 128 kb sectors have the pat tern xxx0000h -xxxffffh. 2.2 device id and cfi (id-cfi) aso there are two traditional methods for systems to identify the t ype of flash memory installed in the system. one has traditiona lly been called autoselect and is now ref erred to as device identificati on (id). the other me thod is called common flash interface (cfi ). for id, a command is used to ena ble an address space overlay wh ere up to 16 word l ocations can be read to get jedec manufacturer identific ation (id), device id , and some configura tion and protection st atus information fro m the flash memory. t he system can use the manufacturer and device ids to select the ap propriate driver software to use with the flash device. cfi also uses a command to enable an address spac e overlay wher e an extendable tabl e of standard info rmation about how the flash memory is organized and oper ates can be read. with this m ethod the driver software does not have to be wr itten with the specifics of each possible memory device in mind. instead the d river software is written in a more general way to handle many different devices but adjusts t he driver behavior based on the information in the cfi table. traditionally these two address spaces have used separate comma nds and were separate overlays. however, the mapping of these two address spaces are non-ove rlapping and so can be combined i n to a single address space and appear together in a single overlay. either of the traditi onal commands used to access (ent er) the autoselect (id) or cfi o verlay will cause the now combi ned id-cfi address map to appear. the id-cfi address map appears within, and overlays the flash a rray data of, the sector selected by the address used in the id -cfi enter command. while the id-cfi aso is entered the content of a ll other sectors is undefined. the id-cfi address map starts a t location 0 of the selected sec tor. locations above the maximu m defined address of the id-cfi aso to the maximum addr ess of the selected sector have undefine d data. the id-cfi enter com mands use the same address and data values used on previous generation memories to access the jedec manufacturer id (auto select) and common flash interface (cfi) informa tion, respectively. see figure 11.16, aso entry timing on page 87 for aso entry timing requirements. for the complete address map see table7.2 onpage58 . table 2.4 s29gl128s sector and m emory address map sector size (kbyte) sector count sector range address range (16-bit) notes 128 128 sa00 0000000h-000ffffh sector starting address ::C sa127 07f0000h-07fffffh sector ending address table 2.5 id-cfi address map overview word address description read / write (sa) + 0000h to 000fh device id (traditional autoselect values) read only (sa) + 0010h to 0079h cfi data structure read only (sa) + 0080h to ffffh undefined read only
document number: 001-98285 rev. *o page 9 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 2.3 device id and common flash in terface (id-cfi) aso map auto motive only fab lot # + wafe r # + die x coordinate + die y coordinate gives a unique id fo r each device. 2.3.1 device id the joint electron device engin eering council (jedec) standard jep106t defines the manufacturer id for a compliant memory. common industry usage defined a method and format for reading t he manufacturer id and a devic e specific id from a memory device. the manufacturer and device id information is primarily intended for programming equipmen t to automatically match a device with the corresponding p rogramming algorithm. cypress ha s added additional fiel ds within this 32-byte address space. the original industry format was structured to work with any me mory data bus width e. g. x8, x16 , x32. the id code values are traditionally byte wide but are l ocated at bus width address bo undaries such that incrementi ng the device addr ess inputs will read successive byte, word, or double w ord locations with the id cod es always located in the least si gnificant byte location of the data bus. because the device data bus is word wide each code byte is located in the lower half of each word location. the original industry format made the high order byte always 0. cypress has modified the format to use both bytes in some words of the addr ess space. for the detail descripti on of the device id address map see table 7.2 on page 58 . 2.3.2 common flash memory interface the jedec common flash interface (cfi) specification (jesd68.01 ) defines a standardized data str ucture that may be read from a flash memory device, which allows vendor-specified software alg orithms to be used for entire families of devices. the data str ucture contains information for system configuration such as various e lectrical and timing parameters, and specia l functions supporte d by the device. software support ca n then be device-independent, de vice id-independent, and forward-and-backward-compatible for entire flash device families. the system can read cfi informati on at the addresses within the selected sector as shown in device id and common flash interface (id-cfi) aso map on page 58 . like the device id inf ormation, cfi informa tion is structured t o work with any memor y data bus width e. g. x8, x16, x32. the c ode values are always byte wide but a re located at data bus width a ddress boundaries such that incrementing the device address rea ds successive byte, word, or double w ord locations with the codes always located in the least sign ificant byte location of the da ta bus. because the data bus i s word wide each code byte is located in the lower half of each word location and th e high order byte is always 0. for further info rmation, please refer to the cypress cfi specification, version 1.4 (or later), and the jedec publications jep137-a and jesd68.01 . please contact jedec ( http://www.jedec.org ) for their standards and the c ypress cfi specification may be found at the cypress website ( http://www.cypress. com/cypressappnotes ) at the time of this documents publication), or contact the l ocal cypress sales office l isted in the website. word address data field # of bytes data format example of actual data hex read out of example data (sa) + 0080h size of electronic marking 1 hex 19 0013h (sa) + 0081h revision of electronic marking 1 hex 1 0001h (sa) + 0082h fab lot # 7 ascii ld87270 004ch, 0044h, 0038h, 0037h, 0032h, 0037h, 0030h (sa) + 0089h wafer # 1 hex 23 0017h (sa) + 008ah die x coordinate 1 hex 10 000ah (sa) + 008bh die y coordinate 1 hex 15 000fh (sa) + 008ch class lot # 7 ascii br33150 0042h, 0052h, 0033h, 0033h, 0031h, 0035h, 0030h (sa) + 0093h reserved for future 13 n/a n/a undefined
document number: 001-98285 rev. *o page 10 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 2.4 status register aso the status register aso contains a single word of registered vo latile status for embedded algori thms. when the status register read command is issued, the curr ent status is captured (by the rising edge of we#) into the regi ster and the aso is entered. t he status register conten t appears on all word l ocations. the firs t read access exits the status r egister aso (with the rising ed ge of ce# or oe#) and returns to the ad dress space map in use when th e status register read comma nd was issued. write commands will not exit the status register aso state. 2.5 data polling status aso the data polling statu s aso contains a single word of volatile memory indicating the progress of an ea. the data polling statu s aso is entered immediately follow ing the last write cycle of an y command sequence that initiates an ea. commands that initiate an ea are: ? word program ? program buffer to flash ? chip erase ? sector erase ? erase resume / program resume ? program resume enhanced method ? blank check ? lock register program ? password program ? ppb program ? all ppb erase engineering note: the reset a nd write buffer abor t reset comman ds require very short time to e xecute so data polling is not supported for these commands.t he data polling status word appea rs at all word locations in the device address space. when an ea is completed the data polling status aso is exited and the d evice address space returns to t he address map mode where the ea was started. 2.6 secure silicon region aso the secure silicon region (ssr) pr ovides an extra flash memory area that can be programmed onc e and permanently protected from further changes i. e. it is a one time progr am (otp) area. the ssr is 1024 bytes in length. it consists of 512 bytes for factory lock ed secure silicon region and 512 bytes for customer locked secu re silicon region. the sector address supplied during the secure silicon entry com mand selects the flash memory array sector that is overlaid by the secure silicon region address map. see figure 11.16, aso entry timing on page 87 for aso entry timing requirements. the ssr is overlaid starting at location 0 in the selected sector. use of the sector 0 address is recommended for future compatibility . while the ssr aso is entered the content of all other sectors is undefine d. locations above the maximum defined address of the ssr aso t o the maximum address of the sele cted sector hav e undefined data. table 2.6 secure silicon region word address range content size (sa) + 0000h to 00ffh factory lo cked secure silicon region 512 by tes (sa) + 0100h to 01ffh customer locked secure silicon region 512 b ytes (sa) + 0200h to ffffh undefined 127 kbytes
document number: 001-98285 rev. *o page 11 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 2.7 sector protection control 2.7.1 lock register aso the lock register aso contains a single word of ot p memory. whe n the aso is entered the lock register appears at all word locations in the device address space. see figure 11.16, aso ent ry timing on page 87 for aso entry timing requirements. however, it is recommended to r ead or program the lock register only at location 0 of the device address space for future compatibility. 2.7.2 persistent prot ection bits (ppb) aso the ppb aso contains one bit of a flash memory array for each s ector in the device. when the ppb aso is en tered, the ppb bit for a sector appears in the leas t significant bit (lsb) of each address in the sector. see figure 11.16, aso entry timing on page 87 for aso entry timing requirement s. reading any address in a se ctor displays data where t he lsb indicates the non- volatile protection status for that sector. however, it is reco mmended to read or program the ppb only at address 0 of the sec tor for future compatibility. if the bit is 0 the sector is protected a gainst programming and erase o perations. if the bit is 1 the se ctor is not protected by the ppb. the sector m ay be protected by other feat ures of asp. 2.7.3 ppb lock aso the ppb lock aso contains a single bit of volatile memory. the bit controls whether the bits in the ppb aso may be programmed or erased. if the bit is 0 the ppb aso is protec ted against pro gramming and erase op erations. if the bit is 1 the ppb aso is n ot protected. when the ppb lock aso is entered the ppb lock bit ap pears in the least significant b it (lsb) of each address in the device address space. see figure 11.16, aso entry timing on page 87 for aso entry timing requi rements. however, it is recommended to read or program the ppb lock only at address 0 o f the device for future compatibility. 2.7.4 password aso the password aso contains four w ords of otp memory. when the as o is entered the passw ord appears starti ng at address 0 in the device address space. see figure 11.16, aso entry timing on page 87 for aso entry timing requirements. all locations above the forth word are undefined. 2.7.5 dynamic protect ion bits (dyb) aso the dyb aso contains one bit of a volatile memory array for eac h sector in the device. when the dyb aso is entered, the dyb bi t for a sector appears in the leas t significant bit (lsb) of each address in the sector. see figure 11.16, aso entry timing on page 87 for aso entry timing requirement s. reading any address in a se ctor displays data where t he lsb indicates the non- volatile protection status for t hat sector. however, it is reco mmended to read, set, or clear the dyb only at address 0 of the sector for future compatibility. if the bit is 0 the sector is protected a gainst programming and erase o perations. if the bit is 1 the se ctor is not protected by the dyb. the sector m ay be protected by other feat ures of asp. 2.8 ecc status aso the system can access the ecc stat us aso by issuing the ecc sta tus entry command sequence during read mode. the ecc status aso provides the status of a single bit error correction when reading the selected page. section 5.3, automatic ecc on page 22 describes the ecc function in more detail. see figure 11.16, aso entry timing on page 87 for aso entry timing requirements. the ecc status aso allows the following activities: ? read ecc status for t he selected page. ? aso exit. 2.8.1 ecc status the contents of the ecc status a so indicates, for the selected ecc page, whether ecc protecti on has corrected an error in the eight-bit error correction code o r the 16 words of data in the ecc page. the address specified in the ecc status read command, provided in table7.1 onpage55 selects the ecc page.
document number: 001-98285 rev. *o page 12 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 2.7 ecc status word C upper byte bit151413121110 9 8 name rfu rfu rfu rfu rfu rfu rfu rfu valuexxxxxxxx table 2.8 ecc status word C lower byte bit 7 6 5 4 3 2 1 0 name rfu rfu rfu rfu rfu single bit error corrected in the 8-bit error correction code single bit error corrected in 16 words of data rfu value x x x x x 0=no error corrected 1=single bit e rror corrected 0=no error corrected 1=single bit error corrected x
document number: 001-98285 rev. *o page 13 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 3. data protection the device offers several featur es to prevent malicious or acci dental modification of any sector via hardware means. 3.1 device protection methods 3.1.1 power-up write inhibit reset#, ce#, we#, and, oe# are ignored during po wer-on reset (p or). during por, the device can not be sel ected, will not accept commands on the rising ed ge of we#, and doe s not drive o utputs. the host interface c ontroller (hic) and embedded algorithm controller (eac) are reset to their standby states, r eady for reading array data, duri ng por. ce# or oe# must go to v ih before the end of por (t vcs ). at the end of por the device conditions are: ? all internal configuration information is loaded, ? the device is in read mode, ? the status register is at default value, ? all bits in the dyb aso are se t to un-protect all sectors, ? the write buffer is loaded with all 1s, ? the eac is in the standby state. 3.1.2 low v cc write inhibit when v cc is less than v lko , the hic does not accept any wri te cycles and the eac resets. this protects data during v cc power-up and power-down. the system must provide the proper signals to t he control pins to prevent unintentional writes when v cc is greater than v lko . 3.2 command protection embedded algorithms are initiated by writing command sequences into the eac command memory. the command memory array is not readable by the host system a nd has no aso. each host inter face write is a command or part of a command sequence to the device. the eac examines the addr ess and data in each write tra nsfer to determine if the writ e is part of a legal command sequence. when a legal command s equence is complete the eac wil l initiate the ap propriate ea. writing incorrect address or dat a values, or writing them in an improper sequence, will generally result in the eac returning to its standby state. however, such an improper command sequence may p lace the device in an unknow n state, in which case the system must write the reset command, or possibly provide a hard ware reset by driving the reset# signal low, to return the eac to its standby state, ready for random read. the address provided in each write may contain a bit pattern us ed to help identify the write as a command to the device. the u pper portion of the address may also select the sector address on wh ich the command operation is to be performed. the sector addres s (sa) includes a max through a16 flash address bits (system byte address signals a max through a17). a command bit pattern is located in a10 to a0 flash address bi ts (system byte address signals a1 1 through a1). the data in each write may be: a bit pattern use d to help ident ify the write as a command, a co de that identifie s the command operation to be performed, or supply informati on needed to perf orm the operation. see table7.1 onpage55 for a listing of all commands accepted by the device. 3.3 secure silicon region (otp) the secure silicon region (ssr) pr ovides an extra flash memory area that can be programmed onc e and permanently protected from further changes i. e. it is a one time program (otp) area. the ssr is 1024 bytes in length. it consists of 512 bytes for fa ctory locked secure silicon region and 512 bytes for customer locked s ecure silicon region.
document number: 001-98285 rev. *o page 14 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 3.4 sector protection methods 3.4.1 write protect signal if wp# = v il , the lowest or highest address se ctor is protected from progra m or erase operations ind ependent of any other asp configuration. whether it is t he lowest or highest sector depen ds on the device orde ring option (model) selected. if wp# = v ih , the lowest or highest add ress sector is not pro tected by the wp# si gnal but it ma y be protected by other a spects of asp configurat ion. wp# has an internal pull-up; w hen unconnected, wp# is at v ih . 3.4.2 asp advanced sector protection (asp) is a set of independent hardwa re and software methods used to disable or enable programming or erase operations, individually , in any or all sectors. this section describes the va rious methods of protecting data stored in the memory array. an overview of these methods is shown in figure 3.1 . figure 3.1 advanced sector protection overview every main flash array sector has a non-volatile (ppb) and a vo latile (dyb) protection bit a ssociated with it. when either bit is 0, the sector is protected from pro gram and erase operations. the ppb bits are prote cted from program and erase when the ppb lock bit is 0. there are two me thods for managing the state of the ppb lock bit, persistent prote ction and password protection . password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 4 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 5,6 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 7,8,9 7. 0 = sector protected, 1 = sector unprotected. 8. protect effective only if corresponding ppb is ?1? (unprotected). 9. volatile bits: defaults to user choice upon power-up (see ordering options). 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset (to ?0? if in password mode). 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock or application of the password. 4. n = highest address sector.
document number: 001-98285 rev. *o page 15 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s the persistent protection meth od sets the ppb lock to 1 during por or hardware rese t so that the ppb bits a re unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb bits. there is no command in the persistent protection method to set the ppb lock bit therefore the ppb loc k bit will remain at 0 until the next power-off or hardware res et. the persistent protection method all ows boot code the option of cha nging sector protection by progr amming or erasing the ppb, then protecting the ppb from further change for the remainder of nor mal system operation by cleari ng the ppb lock bi t. this is sometimes called boot-code con trolled sector protection. the password method c lears the ppb lock bit t o 0 during por or hardware reset to protect the ppb. a 64- bit password may be permanently programmed and hidden for the password method. a co mmand can be used to provide a password for comparison with the hidden password. if the passw ord matches the ppb lock bit i s set to 1 to unprot ect the ppb. a command can be used to clear the ppb lock bit to 0. the selection of the ppb lock manag ement method is made by prog ramming otp bits in t he lock register so as to permanently select the method used. the lock register also contains o tp bits, for protecting the ss r. the ppb bits are erased so that all main flash a rray sectors ar e unprotected when shipped from cypress. the secured silicon region can be factory protected or left u nprotected depending o n the ordering optio n (model) ordered. 3.4.3 ppb lock the persistent protection bit lock is a volatile bit for protec ting all ppb bits. when cleared to 0, it locks a ll ppbs and whe n set to 1, it allows the ppbs to be chang ed. there is only one ppb lock bi t per device. the ppb lock command is used to clear the b it to 0. the ppb loc k bit must be cleared to 0 only after all the ppbs are configur ed to the desired settings. in persistent protect ion mode, the ppb lock is set to 1 during por or a hardware reset. when cleared, no software command sequence can set the ppb lock, only another hardware reset or p ower-up can set the ppb lock bit. in the password protection mode, the ppb lock is cleared to 0 d uring por or a hardware reset. the ppb lock can only set to 1 b y the password unlock command sequenc e. the ppb lock can be clear ed by the ppb lock bi t clear command. 3.4.4 persistent protection bits (ppb) the persistent protection bits (ppb) are located in a separate nonvolatile flash arra y. one of the ppb bits is assigned to eac h sector. when a ppb is 0 its relat ed sector is protected from pr ogram and erase operations. the ppb are programmed individually but must be erased as a group, similar to t he way individual wo rds may be programmed in the main array bu t an entire sector mu st be erased at the same time. preprogramming and verification pri or to erasure are h andled by the eac. programming a ppb bit requires the typical word programming tim e. during a ppb bit programming op eration or ppb bit erasing, data polling status dq6 toggle bit i will toggl e until the oper ation is complete. erasing all the ppbs requires typical sector erase time. if the ppb lock is 0, th e ppb program or erase commands do not execute and time-out without progra mming or erasing the ppb. the protection state of a ppb for a given sector can be verifie d by executing a ppb status read command when entered in the pp b aso. 3.4.5 dynamic protection bits (dyb) dynamic protection bits are vola tile and unique for each sector and can be individually modifi ed. dybs only control protection for sectors that have thei r ppbs erased. by issu ing the dyb set or clear command sequences, the dyb a re set to 0 or cleared to 1, thus placing each sector in the protected or unprotected state respectively, if the ppb for the sector is 1. this f eature allo ws software to easily protect secto rs against inadvertent changes, yet does not prevent the easy removal of protection when chang es are needed. the dyb can be set to 0 or cl eared to 1 as often as needed.
document number: 001-98285 rev. *o page 16 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 3.4.6 sector protection states summary each sector can be in one of t he following prot ection states: ? unlocked C the sector is unprotec ted and protection can be chan ged by a simple command. the protection st ate defaults to unprotected aft er a power cycle or hardware reset. ? dynamically locked C a sector is protected and protection can b e changed by a simple command . the protection state is not saved across a power cycle or hardware reset. ? persistently locked C a sector i s protected and protection can only be changed if the ppb lo ck bit is set to 1. the protection state is non-volatile and saved across a power cycle or hardware reset. changing the protection state requires programming or erase of the ppb bits. 3.4.7 lock register the lock register holds the non-v olatile otp bits for controlli ng protection of the ssr, and determining the ppb lock bit management method (protection mode). the secure silicon region (ssr) protection bits m ust be used wi th caution, as once locked, ther e is no procedure available for unlocking the protect ed portion of the se cure silicon region an d none of the bits in the prote cted secure silicon region memor y space can be modified in any way. once the secure silicon regio n area is protected, any further attempts to program in the are a will fail with status indicating the ar ea being programmed is protec ted. the region 0 indicator bit is located in the lock register at bit location 0 and region 1 in bit location 6. table 3.1 sector protection states protection bit values sector state ppb lock ppb dyb 1 1 1 unprotected - ppb an d dyb are changeable 1 1 0 protected - ppb and dyb are changeable 1 0 1 protected - ppb and dyb are changeable 1 0 0 protected - ppb and dyb are changeable 0 1 1 unprotected - ppb not changeable, dyb is changeable 0 1 0 protected - ppb not changeable, dyb is changeable 0 0 1 protected - ppb not changeable, dyb is changeable 0 0 0 protected - ppb not changeable, dyb is changeable table 3.2 lock register bit default value name 15-9 1 reserved 8 0 reserved 7 x reserved 6 1 ssr region 1 (c ustomer) lock bit 5 1 reserved 4 1 reserved 3 1 reserved 2 1 password protection mode lock bit 1 1 persistent protection mode lock bit 0 0 ssr region 0 (factory) lock bit
document number: 001-98285 rev. *o page 17 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s as shipped from the factory, all devices default to the persist ent protection method, with all sectors unpr otected, when power is applied. the device programmer or host system can then choose w hich sector protection method to use. programming either of the following two, one-time programm able, non-volatile bits, locks the part permanent ly in that mode: ? persistent protection mode lock bit (dq1) ? password protection mode lock bit (dq2) if both lock bits are selected to be programmed at the same tim e, the operation will abort. once the password mode lock bit is programmed, the persistent mode lock bit is permanently disable d and no changes to the protection scheme are allowed. similarl y, if the persistent mode lock bit is programmed, the password mod e is permanently disabled. if the password mode is to be chosen, the password must be prog rammed prior to setting the corresponding lock register bit. se tting the password protection mode lock bit is programmed, a power cy cle, hardware reset, or ppb lock bit set command is required to set the ppb lock bit to 0 to protect the ppb array. the programming time of the lock register is the same as the ty pical word programming time. during a lock register programming ea, data polling status dq6 toggl e bit i will toggle until the programming has completed. the system can also determine the st atus of the lock register programming by reading the st atus register . see status register on page 34 for information on these status bits. the user is not required to program dq2 or dq1, and dq6 or dq0 bits at the same time. this allows the user to lock the ssr bef ore or after choosing the device pro tection scheme. when programmin g the lock bits, the reserv ed bits must be 1 (masked). 3.4.8 persistent protection mode the persistent protection meth od sets the ppb lock to 1 during por or hardware rese t so that the ppb bits a re unprotected by a device reset. there is a command to clear the ppb lock bit to 0 to protect the ppb. t here is no command i n the persistent protection method to s et the ppb lock bit to 1 therefore the pp b lock bit will remain at 0 until the next power-off or hardwar e reset. 3.4.9 password protection mode 3.4.9.1 ppb password protection mode ppb password protection mode allows an even h igher level of sec urity than the persistent sect or protection mode, by requiring a 64-bit password for setting th e ppb lock. in addi tion to this p assword requirement , after power up and r eset, the ppb lock is cleared to 0 to ensure protection at power-up. successful execu tion of the password unlock co mmand by entering the entire password sets the ppb lock to 1, a llowing for sector ppb modifi cations. password protection notes: ? the password program command is o nly capable of programming 0s . ? the password is all 1s when ship ped from cypress. it is locate d in its own memory space and is accessible through the use of the password program a nd password read commands. ? all 64-bit password combinations are valid as a password. ? once the password is programmed and verified, the password mode locking bit must be set in order to prevent reading or modification of the password. ? the password mode lock bit, onc e programmed, prevents reading t he 64-bit password on the data bus and further password programming. all further program and read commands to the password region are dis abled (data is read as 1's) and these commands are ignored. there is no means to verify wha t the password is after the password protection mode lock bit is programmed. password verification is only allowed b efore selecting the password protection mode. ? the password mode lock bit is not erasable. ? the exact password must be enter ed in order for the unlocking f unction to occur. ? the addresses can be loaded in any order but all 4 words are re quired for a successf ul match to occur.
document number: 001-98285 rev. *o page 18 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s ? the sector addresses and word line addresses are compared while the password address/data are loaded. if the sector address don't match than the error will be reported at the end of that write cycle. the status r egister will return to the rea dy state with the program status bi t set to 1, program status regi ster bit set to 1, and write buf fer abort status bit set to 1 indicating a failed programmi ng operation. it is a failure to c hange the state of the ppb lock bi t because it is still protect ed by the lack of a valid password. the data polling status will r emain active, with dq7 set to the complement of the dq7 bit in the last word of the password unlock command, a nd dq6 toggling. ry/by# will remain low. ? the specific address and data are compared after the program bu ffer to flash command has been given. if they don't match to the internal set value than the status register will r eturn to the ready state with the program status bit set to 1 a nd program status register bit set t o 1 indicating a failed progra mming operation. it is a failure to change the state of the ppb lock bit because it is still pr otected by the lack of a valid p assword. the data polling status will remain active, with dq7 s et to the complement of the dq7 bit in the last word of the passwo rd unlock command, and dq6 toggling. ry/by# will remain low. ? the device requires approximately 100 s for set ting the ppb lo ck after the valid 64-bit pas sword is given to the device. ? the password unlock command cann ot be accepted any faster than once every 100 s 20 s . this makes it take an unreasonably long time (58 millio n years) for a hacker to run t hrough all the 64-bit combinati ons in an attempt to correctly match a password. the ea status checking methods may be used to determine when the eac is ready to accept a new password command. ? if the password is lost after se tting the password mode lock bi t, there is no way to clear the ppb lock.
document number: 001-98285 rev. *o page 19 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 4. read operations 4.1 asynchronous read each read access may be made to any locatio n in the memory (ran dom access). each random access is self-timed with the same latency from ce# or address to valid data (t acc or t ce ). 4.2 page mode read each random read accesses an entire 32-byte page in parallel. s ubsequent reads within the same page have faster read access speed. the page is selected by the higher address bits (a max -a4), while the specifi c word of that page is selected by the l east significant address bits a3-a0. t he higher address bits are kep t constant and only a3-a0 changed to select a different word in the same page. this is an asynch ronous access with data appearing o n dq15-dq0 when ce# remains low, oe# remains low, and the asynchronous page access time (t pacc ) is satisfied. if ce# goes high and returns low for a subseque nt access, a random read access is performed and time is required (t acc or t ce ).
document number: 001-98285 rev. *o page 20 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5. embedded operations 5.1 embedded algorithm controller (eac) the eac takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change the no n-volatile memory state. this frees the host system from any need to manage t he program and erase processes. there are four eac operation categories: ? standby (read mode) ? address spac e switching ? embedded algorithms (ea) ? advanced sector prote ction (asp) management 5.1.1 eac standby in the standby mode current consu mption is great ly reduced. the eac enters its st andby mode when no command is being processed and no embedded algorit hm is in progress. if the devi ce is deselected (ce# = high) during an embedded algorithm, the device still dra ws active current until the operation is completed (i cc3 ). i cc4 in dc characteristics on page 72 represents the standby curren t specification w hen both the hos t interface and eac are in their standby state. 5.1.2 address space switching writing specific address and da ta sequences (command sequences) switch the memory device addr ess space from the main flash array to one of the addre ss space overlays (aso). embedded algorithms operate on the information visible in the c urrently active (entered) aso. the system continues to have acc ess to the aso until the system issues an aso exit command, perform s a hardware reset, or until pow er is removed from the device. an aso exit command switches fr om an aso back to the main flash array address space. the c ommands accepted when a particular aso is entered are l isted between the aso enter and exit commands in the command definitions table. see command summary on page 55 for address and data requirem ents for all command sequences. 5.1.3 embedded algorithms (ea) changing the non-volatile data in the memory array requires a c omplex sequence of operations that are called embedded algorithms (ea). the algorithm s are managed ent irely by the dev ice internal embedded algorit hm controller (eac). the main algorithms perform programming an d erasing of the main array da ta and the asos. the host system writes command codes to the flash device address space. the eac receives the commands, perf orms all the necessary steps t o complete the command, and provides status information during the progress of an ea.
document number: 001-98285 rev. *o page 21 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.2 program and erase summary flash data bits are erased in parallel in a large group called a sector. the erase o peration places each data bit in the secto r in the logical 1 state (high). flash data bits may be individually pro grammed from the erased 1 state to the programmed logical 0 (lo w) state. a data bit of 0 cannot be programmed back to a 1. a succ eeding read shows that the data is still 0. only erase operatio ns can convert a 0 to a 1. programming t he same word location more tha n once with different 0 bits will result in the logical and of the previous data and the new data being programmed. the duration of progr am and erase operations is shown in embedded algorithm perfo rmance table on page 43 . program and erase operat ions may be suspended. ? an erase operation may be susp ended to allow either programming or reading of another sector (not in the erase sector). no other erase operation can be started during an erase suspend . ? a program operation may be suspe nded to allow reading of anothe r location (not in the line being programmed). ? no other program or erase opera tion may be started during a sus pended program operation - program or erase commands will be ignored during a susp ended program operation. ? after an intervening program ope ration or read access is comple te the suspended erase or p rogram operation may be resumed. the resume can happen at any time after the suspend as suming the device is not in the proc ess of executing another command. ? program and erase operations may be interrupted as often as nec essary but in order for a pr ogram or erase operation to progress to completion there must be some periods of time betwe en resume and the next suspend commands greater than or equal to t prs or t ers in embedded algorithm perf ormance table on page 43 . ? when an embedded algorithm (ea) is complete, the eac returns to the operation state and address space from which the ea was started (erase s uspend or eac standby). the system can determine the stat us of a program or erase opera tion by reading the status regis ter or using data polling statu s. refer to status register on page 34 for information on thes e status bits. refer to data polling status on page 35 for more information. any commands written to the device during the embedded program algorithm are ignored except the program suspend, and status read command. any commands written to the dev ice during the em bedded erase al gorithm are ignored except er ase suspend and status read command. a hardware reset immediately te rminates any in progress program / erase operation and ret urns to read mode after t rph time. the terminated operation should be rein itiated once the device has returned to the idle state , to ensure data integrity. for performance and reliability r easons reading and programming is internally done on full 32-byte pages. i cc3 in dc characteristics on page 72 represents the active current s pecification for a write (embed ded algorithm) operation. 5.2.1 program granularity the s29gl-s supports two methods of programming, word or write buffer programming. each page can be programmed by either method. pages programmed by dif ferent methods may be mixed with in a line for the industrial t emperature versi on (-40c to +85c). for the in-cabin version (-40c to +105c) the device w ill only support one programming operation on each 32-byte page between erase operations and sing le word programming command is not supported. word programming examines the d ata word supplied by the command and programs 0s in the add ressed memory a rray word to match the 0s in t he command data word. write buffer programming examines the write buffer and programs 0s in the addressed memory array pages to match the 0s in th e write buffer. the write buffer does not need to be completely f illed with data. it is allowed to p rogram as litt le as a single bit, several bits, a single word, a few words, a page, multiple pages, or th e entire buffer as one programmi ng operation. use of the write buffer method reduces host system over head in writing program commands and reduces memory devic e internal overhead in programming operations to make wri te buffer programming more ef ficient and thus faster than pro gramming individual words with the word programming command.
document number: 001-98285 rev. *o page 22 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.2.2 incremental programming the same word location may be prog rammed more than once, by eit her the word or write buffe r programming methods, to incrementally change 1s to 0s . note that if additional progra mming is performed on a page its ecc coverage is disabled. 5.3 automatic ecc 5.3.1 ecc overview the automatic ecc feature works transparently with normal progr am, erase, and read operations . as the device transfers each page of data from the write buffe r is to the memory array, inte rnal ecc logic programs ecc code for the page into a portion of the memory array that is not visibl e to the host system. the device evaluates the page data and the ecc code during each initial p age access. if needed, the internal ecc logic corrects a one bit er ror during the initial access. programming more than once to a particular page will disable th e ecc function for that page. the ecc function will remain disa bled for that page until t he next time the host system erases the se ctor containing that page. the host system may read data stored in that page following multiple progr amming operations; however, e cc is disabled and an error in that page will no t be detected o r corrected. 5.3.2 program and erase summary for performance and reliability reasons, gl-s devices perform r eading and programming on full 32-byte pages in parallel. the g l-s device provides ecc on each page by adding an ecc code to each page when it is first programmed. the ecc code is automatic and transparent to the host system. 5.3.3 ecc implementation each 32-byte page in the main flash array and otp regions featu res an associated ecc code. the ecc code, in combination with ecc logic, is able to detect and correct any single bit error f ound in a page during a read access. the first write buffer program operation applied to a page prog rams the ecc code for that page. subsequent programming operations that occur more than once on a particular page disab le the ecc function for that pa ge. this allows bit or word programming; however, note that multiple programming operations to the same page will disable the ecc functi on on the page where incremental programming o ccurs. an erase o f the sector co ntaining a page with ecc disa bled will re-enable the ecc function for that page. the ecc function is automatic and transparent to the user. the transparency of the automatic e cc function enhances data integr ity for typical programming operati ons that write data once to each page. the ecc function also fa cilitates software compatibility to previous generations of gl family products by allowing single w ord programming and bit walking w here the same page or word is programmed more than once. when a page has automatic ecc disabl ed, the ecc function will not detect or co rrect an error on a data read from that page. 5.3.4 word programming word programming programs a sing le word anywhere in the main fl ash memory array. programming multiple words in the same 32-byte page disables automatic ecc protection on that page. a sector erase of the sector conta ining that page will re-enable automatic ecc following word programming on that page. 5.3.5 write buffer programming each write buffer program opera tion allows for programming of 1 bit up to 512 bytes. a 32-byte page is the smallest program granularity that features automatic ecc protection. programming the same page more than once will disable the automatic ecc on that page. cypress recommends that a write buffer programming o peration program multiple pages in an operation and write each page only once. this keeps the au tomatic ecc protection enabled on each page. for the very bes t performance, program in full lines of 512 bytes aligned on 512-byte boundaries.
document number: 001-98285 rev. *o page 23 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4 command set 5.4.1 program methods 5.4.1.1 word programming word programming is us ed to program a single word anywhere in t he main flash memory array. the word programming command is a four-write-cycle sequence. th e program command sequence is initiated by writing two unlock write cycles, followed by t he program set up command. th e program address and data are written next, which in turn init iate the embedded word progr am algorithm. the sy stem is not required to provide further controls or timing. the device automaticall y generates the program pulses and verifies the programmed cell m argin internally. when the embed ded word program algorithm is complete, the eac then returns to its standby mode. the system can determine the stat us of the progr am operation by using data polling status, re ading the status register, or monitoring the ry/by# output. see status register on page 34 for information on th ese status bits. see data polling status on page 35 for information on these status bits. see figure 5.1 on page 23 for a diagram of the programming operation. any commands other than program suspend written to the device d uring the embedded program algorithm are ignored. note that a hardware reset (reset# = v il ) immediately terminates the pr ogramming operation and returns the device to read mode after t rph time. to ensure data in tegrity, the program command sequence sh ould be reinitiated onc e the device has com pleted the hardware reset operation. a modified version of the word programming command, without unl ock write cycles, is used for prog ramming when ent ered into the lock register, password, and ppb asos. the same command is used to change volatile bits when entered in to the ppb lock, and dyb asos. see table7.1 onpage55 for program command sequences. figure 5.1 word program operation start write program command sequence data poll from system verify word? last addresss? increment address embedded program algorithm in progress programming completed no no yes yes
document number: 001-98285 rev. *o page 24 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.1.2 write buffer programming a write buffer is used to progr am data within a 512-byte addres s range aligned on a 512-byte b oundary (line). thus, a full wri te buffer programming operation mu st be aligned on a line boundary . programming operations of les s than a full 512 bytes may star t on any word boundary but may not cross a line boundary. at the start of a write buffer programming operation all bit locations in the buffer are all 1s (ffffh words) thus any locations not loaded will retain the exis ting data. see product overview on page 4 for information on address map. write buffer programming allows u p to 512 bytes to be programme d in one operation. it is possibl e to program from 1 bit up to 512 bytes in each write buffer programming operation. it is recomme nded that a multiple of pages be written and each page written only once. for the very best performa nce, programming should be done in full lines of 512 bytes aligned on 512-byte boundaries. write buffer programming is sup ported only in the main flash ar ray or the ssr aso. the write buffer programming oper ation is initiated by first wr iting two unlock cycles . this is followed b y a third write cycl e of the write to buffer command with the sector address (sa), in which programming is to occur. next, t he system writes the number of word locations minus 1. this tells the device how many write bu ffer addresses are loaded with data and therefore when to expec t the program buffer to flas h confirm command. the sector address mus t match in the write to buffe r command and the write word count command. the sector to be programmed must be unlocked (un protected). the system then writes the starting address / data combination. this starting address is the fi rst address / data pair to be programmed, and selects the writ e-buffer-line address. the sect or address must match the write to buffer sector address or the operation will abort and return to the initiating state. all su bsequent address / data pairs must be in sequential order. all write buffer addresses must be within the sa me line. if the system attempts to load data outside this range, t he operation will abort and r eturn to the initiating state. the counter decrements for each data load operation. note that while counting down the data writ es, every write is considered to be data being loaded into the write buffer. no commands are possib le during the write buffer loadi ng period. the only way to stop loading the write buffer is to wri te with an address that is ou tside the line of the programmi ng operation. this invalid addre ss will immediately abort the write to buffer command. once the specified number of write buffer locati ons has been lo aded, the system must then write the program buffer to flash command at the sector address. the device then goes busy. the e mbedded program algorithm automatically programs and verifies the data fo r the correct data pattern. the system is n ot required to provide any controls or timings during these ope rations. if an incorrect number of write bu ffer locations have been loaded the operation will abort and ret urn to the initiating state. th e abort occurs when anything other than the program buffer to flash is written when that command is ex pected at the en d of the word count. the write-buffer embedded programming operation can be suspende d using the program suspend command. when the embedded program algorithm is complete, t he eac then returns to the eac standby or erase suspend standby state where the programming operation was started. the system can determine the stat us of the progr am operation by using data polling status, re ading the status register, or monitoring the ry/by# output. see status register on page 34 for information on th ese status bits. see data polling status on page 35 for information on these status bits. see figure 5.2 on page 25 for a diagram of the programming operation. the write buffer programming se quence will be aborted under the following conditions: ? load a word count value great er than the buffer size (255). ? write an address that is outside t he line provided in the write to buffer command. ? the program buffer to flash comm and is not issued after the wri te word count number o f data words is loaded. when any of the conditions that cause an abort of write buffer command occur the abort will happen immediately after the offen ding condition, and will indicate a p rogram fail in the status regis ter at bit location 4 (psb = 1) due to write buffer abort bit l ocation 3 (wbasb = 1). the next s uccessful program ope ration will clear t he failure status or a clear status register may be issued to c lear the psb status bit. the write buffer programming seq uence can be stopped by the fol lowing: hardware reset or power cycle. however, these using either of these methods may le ave the area being programmed in an intermediate state with invalid or unstable data values. in this case the same area will need to be reprogrammed with the same d ata or erased to ensure data values are properly programmed or erased.
document number: 001-98285 rev. *o page 25 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 5.2 write buffer programming operation with data polling status notes: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 2. if this flowchart location was reached because dq5 = 1, then the device failed. if this flowchart location was reached becaus e dq1 = 1, then the write buffer operation was aborted. in either case the proper reset command must be written to the device to return the device to read mode. write-buffer-programming- abort-rest if dq1 = 1, either software reset or write-buffer-programming-abort-reset if dq5 = 1. 3. see table 7.1, command definitions on page 55 for the command sequence as required for write buffer programm ing. 4. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ?write to buffer? command sector address write ?word count? to program - 1 (wc) sector address write starting address/data wc = 0? abort write to buffer operation? write to a different sector address write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. write next address/data pair wc = wc - 1 write program buffer to flash confirm, sector address read dq7-dq0 with addr = last loaded address dq7 = data? dq5 = 1? dq1 = 1? read dq7-dq0 with addr = last loaded address dq7 = data? fail or abort (note 2) pass no yes (note 4) no no no no no yes yes yes yes yes
document number: 001-98285 rev. *o page 26 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 5.3 write buffer programming oper ation with status register notes: 1. see table 7.1, command definitions on page 55 for the command sequence as required for write buffer programm ing. 2. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. write ?write to buffer? command sector address write ?word count? to program - 1 (wc) sector address write starting address/data wc = 0? abort write to buffer operation? write to a different sector address write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. write next address/data pair wc = wc - 1 write program buffer to flash confirm, sector address read status register drb sr[7] = 0? wbasb sr[3] = 1? psb sr[4] = 0? program fail program successful no yes (note 2) no no no yes yes yes no yes program aborted during write to buffer command slsb sr[1] = 0? no yes sector locked error program fail
document number: 001-98285 rev. *o page 27 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s legend: sa = sector address (non-sector address bits are don't care. an y address within the sector is sufficient.) wbl = write buffer location (must be within the boundaries of t he write-buffer-line specified by the starting address.) wc =word count pd = program data 5.4.2 program suspend / program resume commands the program suspend command allows the system to i nterrupt an e mbedded programming operation so that data can read from any non-suspended line. when the program suspend command is wri tten during a programming process, the device halts the programming operation within t psl (program suspend latency) and u pdates the status bits. address es are don't-cares when writing the program suspend command. there are two commands available for program suspend. the legac y combined erase / program suspend command (b0h command code) and the separate program suspend command (51h command cod e). there are also two commands for program resume. the legacy combined erase / program r esume command (30h command cod e) and the separate progr am resume command (50h command code). it is recommended t o use the separate program su spend and resume commands for programming and use the legacy combined command only for erase suspend and resume. after the programming operation has been suspended, the system can read array data from any non-suspended line. the program suspend command may also be iss ued during a programming operati on while an erase is suspended. in this case, data may be read from any addresse s not in erase suspen d or program suspend . after the program resume command is written, the device reverts to programming and the status b its are updated. the system can determine the status of the pr ogram operation by reading the st atus register or using data polling. refer to status register on page 34 for information on these status bits. refer to data polling status on page 35 for more information. accesses and commands that are v alid during progr am suspend are : ? read to any other non-er ase-suspended sector ? read to any other non-program-suspended line ? status read command ? exit aso or command set exit ? program resume command table 5.1 write buffer programming command sequence sequence address data comment issue unlock command 1 555/aaa aa issue unlock command 2 2aa/555 55 issue write to buffer command at sector address sa 0025h issue number of locations at se ctor address sa wc wc = number of words to program - 1 example: wc of 0 = 1 words to pgm wc of 1 = 2 words to pgm load starting address / data pair starting address pd selects write-buffer-page and loads first address/data pair. load next address / data pair wbl pd all addresses must be within the sele cted write-buffer- page boundaries, and have to be loaded in sequential order. load last address/data pair wbl pd all addresses must be within the sele cted write-buffer- page boundaries, and have to be loaded in sequential order. issue write buffer program confirm at sector address sa 0029h this command must follow the last write buffer location loaded, or the operation will abort. device goes busy.
document number: 001-98285 rev. *o page 28 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s the system must write the program resume command to exit the pr ogram suspend mode and c ontinue the programming operation. further writes of the program resume command are ign ored. another program suspend c ommand can be written after the device has resumed programming. program operations can be interr upted as often as necessary but in order for a program operation to progress to c ompletion the re must be some periods of time between resume and the next suspen d command greater than or equal to t prs in embedded algorithm controller (eac) on page 20 . program suspend and resume is not supported while entered in an aso. while in program suspend entry into aso is not supported. 5.4.3 blank check the blank check command will confirm if the selected main flash array sector is erased. the blank check command does not allow for reads to the array during the blank check. reads to the arr ay while this command is execu ting will return unknown data. to initiate a blank check on a se ctor, write 33h t o address 555 h in the sector, while the eac is in the standby state the blank check command may not be written while the device is actively programming o r erasing or suspended. use the status regist er read to confirm if the device is still busy and when complete if the sector is blan k or not. bit 7 of the status register will show if the device is performing a blank check (s imilar to an erase oper ation). bit 5 of the status register wil l be cleared to 0 if the sector is erased and set to 1 if not erased . as soon as any bit is found to no t be erased, the device will h alt the operation an d report the results. once the blank check is complet ed, the eac will return to the s tandby state. 5.4.4 erase methods 5.4.4.1 chip erase the chip erase function erases t he entire main flash memory arr ay. the device does not require the system t o preprogram prior to erase. the embedded erase algorith m automatically programs and verifies the entire memory for a n all 0 data pattern prior to electrical erase. after a successf ul chip erase, all locations within the device co ntain ffffh. the system is not required to provide any controls or timing s during these operat ions. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set up command. two additional unlock write cycle s are then followed by the chi p erase command, which in turn invokes the embedded erase algori thm. when we# goes high, at th e end of the 6th cycle , the ry/by# goes low. when the embedded erase algorithm is complete, the eac returns to the standby state. note t hat while the embedded erase operation is in progress, the s ystem can not read data from the device. the system can determine the status of the erase opera tion by reading ry/by#, the status r egister or using data polling. r efer to status register on page 34 for information on these status bits. refer to data polling status on page 35 for more information. once the chip erase operation has begun, only a status read, ha rdware reset or power cycle are valid. all other commands are ignored. however, a hardware rese t or power cycle immediately t erminates the erase operation an d returns to read mode after t rph time. if a chip erase operation is terminated, the chip erase command sequence must be rein itiated once the device has returned to the idle state to ensure data integrity. see table 5.4 on page 43 , asynchronous write operations on page 82 and alternate ce# controlled w rite operations on page 88 for parameters and timing diagrams. sectors protected by the asp dyb and ppb lock bits will not be erased. see asp on page 14 . if a sector is prot ected during chip erase, chip erase will skip the protected sector and continue w ith next sector erase. the statu s register erase status bit and sector lock bit are not set to 1 by a f ailed erase on a protected sect or.
document number: 001-98285 rev. *o page 29 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.4.2 sector erase the sector erase function erases one sector in th e memory array . the device does not require the system to preprogram prior to erase. the embedded erase algorith m automatically programs and verifies the entire sector for a n all 0 data pattern prior to electrical erase. after a successf ul sector erase, all location s within the erased sector contain ffffh. the system is not req uired to provide any controls or timings during these oper ations. the se ctor erase command sequence is initiated by writing two unlock cycles, followed by a s et up command. two add itional unlock wri te cycles are then followed by t he address of the sector to be erased, and the sector erase com mand. when we# goes high, at th e end of the 6th cycle, the ry/by# goes low. the system can determine the stat us of the erase operation by r eading the status register or using data polling. refer to status register on page 34 for information on these status bits. refer to data polling status on page 35 for more information. once the sector erase operation has begun, the status register read and erase suspend comm ands are valid. all other commands are ignored. however, note that a hardware reset immed iately terminates the erase oper ation and returns to read mode after t rph time. if a sector erase operati on is terminated, the sector er ase command sequence must be reinitiated once the device has reset operation to ensure data integrity. see embedded algorithm controller (eac) on page 20 for parameters and timing diagrams. sectors protected by the asp dyb and ppb lock bits will not be erased. see asp on page 14 . figure 5.4 sector erase operation write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h fail. write reset command to return to reading array. pass. device returns to reading array. perform write operation status algorithm unlock cycle 1 unlock cycle 2 ye s ye s no no done? erase error? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by status register polling or data polling methods.
document number: 001-98285 rev. *o page 30 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.5 erase suspend / erase resume the erase suspend command allows t he system to interrupt a sect or erase operation and then read data from, or program data to, the main flash array. this command is valid only during sector erase or program operation. the erase suspend command is ignore d if written during the chip erase operation. when the erase suspe nd command is written during the sector era se operation, the device r equires a maximum of t esl (erase suspend latency) to suspend the erase operation and update the status bits. after the erase operation has bee n suspended, the part enters t he erase-suspend mode. the system can read data from or program data to the main flash array. reading at any address within era se-suspended sectors produces und etermined data. the system can determine if a sector is activel y erasing or is erase-suspended by reading the status register or using data po lling. refer to status register on page 34 for information on these status bits. refer to data polling status on page 35 for more information. after an erase-suspended program operation is complete, the eac returns to the erase-suspend st ate. the system can determine the status of t he program operation by r eading the status regis ter, just as in the standard program operation. if a program failure occurs during erase suspend the clear or r eset commands will return the device to the erase suspended sta te. erase will need to be resumed and completed before again trying to program the memory array. accesses and commands that are v alid during eras e suspend are: ? read to any other non-suspended sector ? program to any other non-suspended sector ? status register read ? status register clear ? enter dyb aso ? dyb set ? dyb clear ? dyb status read ? exit aso or command set exit ? erase resume command to resume the sector erase opera tion, the system must write the erase resume command. the device will revert to erasing and th e status bits will be updated. furth er writes of the resume comma nd are ignored. anothe r erase suspend comm and can be written after the chip has resumed erasing. erase suspend and resume is not supported while entered in an a so. while in erase suspend entr y into aso is not supported.
document number: 001-98285 rev. *o page 31 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.6 aso entry and exit 5.4.6.1 id-cfi aso the system can access the id-cfi a so by issuing t he id-cfi entr y command sequence during read mode. this entry command uses the sector address (sa) in the command to determine which sector will be overlaid and which sector's protection state is reported in word location 2h. see the detail description table7.2 onpage58 . the id-cfi aso allows the following activities: ? read id-cfi aso, using the same s a as used in the entry command . ? read sector protection state at s ector address (sa) + 2h. locat ion 2h provides volatile information on the current state of sector protection for the sector addressed. bit 0 of the word a t location 2h shows the logical nand of the ppb and dyb bits related to the addressed sector s uch that if the sector is prot ected by either the ppb=0 or the dyb=0 bit for t hat sector the state shown is protected. (1= sec tor protected, 0= sector unpro tected). this protection stat e is shown only for the sa selected when entering id-cfi aso . reading other sa provides un defined data. to read a different sa protection state aso exit command must be used an d then enter id-cfi aso again w ith the new sa. ? aso exit. the following is a c source code example of using the cfi entry and exit functions. refer to the cypress low level driver user's guide (available on www.cypress.com ) for general informa tion on cypress flash memory software deve lopment guidelines. /* example: cfi entry command */ *( (uint16 *)base_addr + 0x55 ) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x00f0; /* write cfi exit command */ 5.4.6.2 status register aso the status register aso contains a single word of registered vo latile status for embedded algori thms. when the status register read command is issued, the curr ent status is captured (by the rising edge of we#) into the regi ster and the aso is entered. t he status register conten t appears on all word l ocations. the firs t read access exits the status r egister aso (with the rising ed ge of ce# or oe#) and returns to the ad dress space map in use when th e status register read comma nd was issued. write commands will not exit the status register aso state. 5.4.6.3 secure silicon region aso the system can access the secure silicon region by issuing the secure silicon region entry command sequence during read mode. this entry comma nd uses the sector a ddress (sa) in the co mmand to determine which sector will be overlaid. the secure silicon region aso a llows the following activities: ? read secure silicon regions. ? programming the customer secure silicon region is allowed using the word or write buffe r programming commands. ? aso exit using legacy secure sili con exit command for backward software compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method.
document number: 001-98285 rev. *o page 32 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.6.4 lock register aso the system can access the lock regi ster by issui ng the lock reg ister entry command sequence during read mode. this entry command does not use a sector a ddress from the en try command. t he lock register appears at w ord location 0 in the device address space. all other locatio ns in the device address space are undefined. the lock register aso allows the following activities: ? read lock register, using device address location 0. ? program the customer lock register using a modified word progra mming command. ? aso exit using legacy command se t exit command for backward sof tware compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method. 5.4.6.5 password aso the system can access the passwor d aso by issui ng the password entry command sequence duri ng read mode. this entry command does not use a sector a ddress from the en try command. t he password appears at word locations 0 to 3 in the device address space. all other locatio ns in the device address space are undefined. the password aso allows the following activities: ? read password, using device address location 0 to 3. ? program the password us ing a modified word programming command. ? unlock the ppb lock bi t with the passwor d unlock command. ? aso exit using legacy command se t exit command for backward sof tware compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method. 5.4.6.6 ppb aso the system can access the ppb aso by issui ng the ppb entry comm and sequence during read mode. this entry command does not use a sector addre ss from the entry co mmand. the ppb bit fo r a sector appears in bit 0 of al l word locations in the sector . the ppb aso allows the fo llowing activities: ? read ppb protection status of a s ector in bit 0 o f any word in the sector. ? program the ppb bit us ing a modified word programming command. ? erase all ppb bits wit h the ppb erase command. ? aso exit using legacy command se t exit command for backward sof tware compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method. 5.4.6.7 ppb lock aso the system can access the ppb lo ck aso by issui ng the ppb lock entry command sequence during read mode. this entry command does not use a sector a ddress from the en try command. t he global ppb lock bi t appears in bit 0 of all word locations i n the device. the ppb lock aso allo ws the following activities: ? read ppb lock protection status in bit 0 of any word in the dev ice address space. ? set the ppb lock bit using a modif ied word programming command. ? aso exit using legacy command se t exit command for backward sof tware compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method.
document number: 001-98285 rev. *o page 33 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.4.6.8 dyb aso the system can access the dyb aso b y issuing the dyb entry comm and sequence during read mode. this entry command does not use a sector addre ss from the entry co mmand. the dyb bit fo r a sector appears in bit 0 of a ll word locations in the sector . the dyb aso allows the f ollowing activities: ? read dyb protection status of a s ector in bit 0 of any word in the sector. ? set the dyb bit using a modifi ed word programming command. ? clear the dyb bit using a modifi ed word programming command. ? aso exit using legacy command se t exit command for backward sof tware compatibility. ? aso exit using the common exit c ommand for all aso - alternativ e for a consist ent exit method. 5.4.6.9 software (command) reset / aso exit software reset is part o f the command set (see table 7.1, command definitions on page 55 ) that also returns the eac to standby state and must be used for the following conditions: ? exit id/cfi mode ? clear timeout bit (dq5) for dat a polling when timeout occurs software reset does not affect ea mode. reset commands are igno red once programming or er asure has beg un, until the operation is complete. software reset does not affect outputs; it serves primarily to return to read mode from an aso mode or from a failed program or erase operation. software reset may cause a return to read mode from undefined s tates that might result from invalid command sequences. however, a hardware reset may be required to return to normal o peration from some undefined states. there is no software reset laten cy requirement. the reset comma nd is executed during the t wph period. 5.4.6.10 ecc status aso the system can access the ecc stat us aso by issuing the ecc sta tus entry command sequence during read mode. the contents of the ecc status aso indicates , for the select ed ecc page, whe ther ecc protection has corrected an error in the eight-bit err or correction code or t he 16 words of dat a in the ecc page. the ecc status aso allows the following activities: ? read ecc status for the selected page.
document number: 001-98285 rev. *o page 34 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.5 status monitoring there are three methods for m onitoring ea status. previous gene rations of the s29gl fl ash family used the methods called data polling and ready/busy# (ry/by# ) signal. these methods are stil l supported by the s29g l-s family. one add itional method is reading the status register. 5.5.1 status register the status of program and erase operations is provided by a sin gle 16-bit status register. the st atus is receiver by writing t he status register read command followed by a read access. when the statu s register read command is issu ed, the current status is captured (by the rising edge of we#) into the register and the aso is entered. the contents of t he status register is aliased (overlaid) on the full memory address space. any valid read ( ce# and oe# l ow) access while in the status register aso will exit the aso (with the rising edge of ce# or oe# for t ceph /t oeph time) and return to the address space map in use when the stat us register read command was issued. the status register contains bit s related to the results - succ ess or failure - of the most r ecently completed embedded algori thms (ea): ? erase status (bit 5), ? program status (bit 4), ? write buffer abort (bit 3), ? sector locked status (bit 1), ? rfu (bit 0). and, bits related to the current state of any in process ea: ? device busy (bit 7), ? erase suspende d (bit 6), ? program suspended (bit 2), the current state bits indicate w hether an ea is in process, su spended, or completed. the upper 8 bits (bits 15:8) are reserved. these have undefined high or low value that can change from one status read to anot her. these bits should be treated as don't care and ignored by any s oftware reading status. the soft reset comman d will clear to 0 bits [5, 4, 1, 0] of the status register if status reg ister bit 3 =0. it will not affec t the current state bits. the clear status register command will clear to 0 t he results related bits of the status register but will not aff ect the current state bits. notes: 1. bits 15 thru 8, and 0 are reserved for future use and may displa y as 0 or 1. these bits should be ignored (masked) when check ing status. 2. bit 7 is 1 when there is no embedded algorithm in progress in the device. 3. bits 6 thru 1 are valid only if bit 7 is 1. 4. all bits are put in their reset status by cold reset or warm reset. table 5.2 status register bit #15:876543210 bit description reserved device ready bit erase suspend status bit erase status bit program status bit write buffer abort status bit program suspend status bit sector lock status bit reserved bit name drb essb esb psb wbasb pssb slsb reset statusx10000000 busy status invalid 0 invalid invali d invalid invalid invalid invalid in valid ready status x1 0=no erase in suspension 1=erase in suspension 0=erase successful 1=erase fail 0=program successful 1=program fail 0=program not aborted 1=program aborted during write to buffer command 0=no program in suspension 1=program in suspension 0=sector not locked during operation 1=sector locked error x
document number: 001-98285 rev. *o page 35 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5. bits 5, 4, 3, and 1 are cleared to 0 by the clear status register command or reset command. 6. upon issuing the erase suspend command, the user must continue to read status until drb becomes 1. 7. essb is cleared to 0 by the erase resume command. 8. esb reflects success or failure of the most recent erase operation. 9. psb reflects success or failure of the most recent program operation. 10. during erase suspend, programming to the suspended sector, will cause program failure and set the program status bit to 1. 11. upon issuing the program suspend command, the user must continue to read status until drb becomes 1. 12. pssb is cleared to 0 by the program resume command. 13. slsb indicates that a program or erase operation failed because the sector was locked. 14. slsb reflects the status of the most recent program or erase operation. 5.5.2 data polling status during an active embedded algorit hm the eac switches to the dat a polling aso to display ea status to any read access. a single word of status informa tion is aliased in all locations of the d evice address space. in the stat us word there ar e several bits to determine the status of an ea. these are referred to as dq bits as they appear on the data bus during a read access while an e a is in progress. dq bits 15 to 8, dq4, and dq0 are reserved and pro vide undefined data. s tatus monitoring sof tware must mask the reserved bits and treat them as don't care. table 5.3 on page 39 and the following subsections describe the functions of the remaining bits. 5.5.2.1 dq7: data# polling the data# polling bit, dq7, indi cates to the host system whethe r an embedded algorithm is in pr ogress or has completed. data# polling is valid after the rising edge of the final we# pulse i n the program or erase command sequence. note that the data# po lling is valid only for the last word being programmed in the write-b uffer-page during write buffer p rogramming. reading data# polli ng status on any word othe r than the last word to be programmed in the write-buffer-page will return false status information. during the embedded program algorithm, the device outputs on dq 7 the complement of the data bit programmed to dq7. this dq7 status also applies to programmi ng during erase suspend. when t he embedded program algorithm is c omplete, the device outputs the data bit programm ed to bit 7 of the las t word programmed. i n case of a program sus pend, the device allo ws only reading arr ay data. if a program address falls within a protected sector, dat a# polling on dq7 is active for a pproximately 20 s, then the d evice returns to reading array data. during the embedded eras e or blank check algorithms, data# poll ing produces a 0 on dq7. when th e algorithm is complete, or if the device enters the erase sus pend mode, data# polling produce s a 1 on dq7. this is analogous t o the complement / true datum output described for the embedd ed program algorit hm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement or '0'. the system must provide a n address within the sector selected for erasure to read valid status information on dq7. after an erase command sequence is written, if the sector selec ted for erasing is pro tected, data# polling on dq7 is active fo r approximately 100 s, then the d evice returns to reading array data. when the system detects dq7 has changed from the complement to true data, it can read valid dat a at dq15-dq0 on the following read cycles. this is because dq7 may change asynchronously with dq6-dq0 while output enable (o e#) is asserted low. this is illustrated in figure 11.17 on page 87 . table5.3 onpage39 shows the outputs for data# polling on dq7. figure5.2 onpage25 shows the data# polling algorit hm use in write buffer programmi ng. valid dq7 data pol ling status may only be read from: ? the address of the las t word loaded into the write buffer for a write buffer programming operation; ? the location of a s ingle word programming operation; ? or a location in a sector be ing erased or blank checked; ? or a location in any sector during chip erase.
document number: 001-98285 rev. *o page 36 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 5.5 data# polling algorithm note: 1. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 5.5.2.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedd ed program or er ase algorithm is in progress or c omplete, or whether the device has entered the program suspend or erase suspend mode. toggle b it i may be read at any address , and is valid after the rising edge of the final we# pulse in the command sequence (prior to t he program or erase operation). during an embedded program or er ase algorithm ope ration, succes sive read cycles to any addre ss cause dq6 to toggle. (the system may use either oe# or ce# to contro l the read cycles). w hen the operation is compl ete, dq6 stops toggling. after an erase command sequence is written, if the sector selec ted for erasing is pro tected, dq6 toggles for approximately 100 s, then the eac returns to standby (read mode). if the selected se ctor is not protected, the embed ded erase algorit hm erases the unprotected sector. the system can use dq6 and dq2 t ogether to deter mine whether a sector is actively erasing or er ase-suspended. when the device is actively erasing (that is, th e embedded erase algorithm is i n progress), dq6 toggles. when the device enters the program suspend mode or erase suspend m ode, dq6 stops t oggling. however , the system must also use dq2 to determine which sectors are erasing, or erase-suspended. alternatively, the system can use dq7 (see dq7: data# polling on page 35 ). dq6 also toggles during the eras e-suspend-program mode, and sto ps toggling once the embedded prog ram algorithm is complete. table 5.3 on page 39 shows the output s for toggle bit i on dq6. figure5.6 onpage37 shows the toggle bit a lgorithm in flowchart form, and the reading toggle bits dq6/dq2 on page 37 explains the algorithm. figure 5.6 on page 37 shows the toggle bit timing diagrams. figure 5.2 on page 25 shows the differences between dq 2 and dq6 in gra phical form. s ee also dq2: toggle bit ii on page 37 . 5.5.2.3 dq3: sector erase timer after writing a sector erase c ommand sequence, the system may r ead dq3 to determine whether o r not erasure has begun. see sector erase on page 29 for more details. after the sector erase command is written, the system should re ad the status of dq7 (data# polling) or dq6 (toggle bit i) to e nsure that the device has accepted th e command sequenc e, and then rea d dq3. if dq3 is 1, the embedded erase algorithm has begun; all further commands (except er ase suspend) are ignored until t he erase operation is complete. table5.3 onpage39 shows the status of dq3 relative t o the other s tatus bits. start read dq7 -dq0 - fail dq7 = data? no yes dq5 = 1? no yes dq7 = data? no yes pass read dq7 -dq0
document number: 001-98285 rev. *o page 37 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.5.2.4 dq2: toggle bit ii toggle bit ii on dq2, when used with dq6, indicates whether a p articular sector is actively e rasing (that is, the embedded era se algorithm is in progress), or whether that sector is erase-susp ended. toggle bit ii is valid after the rising edge of the fina l we# pulse in the command sequence. dq2 toggles when the system reads a t addresses within the secto r selected for erasure. (the system may use either oe# or ce# t o control the read cyc les). but dq2 cannot distinguish whether th e sector is actively erasing o r is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, o r is in erase suspend, but cannot distinguish if the sector is selected for erasure. thus, both status b its are required for sector and mode informati on. refer to table 5.3 on page 39 to compare outputs for dq2 and dq6. figure 5.5 on page 36 shows the toggle bit algorith m in flowchart form, and the reading toggle bits dq6/dq2 on page 37 explains the algorithm. see also figure 5.6 on page 37 shows the toggle bit timing diagram. figure 5.2 on page 25 shows the differences between dq2 and dq6 in graphical form. 5.5.2.5 reading toggle bits dq6/dq2 refer to figure5.5 onpage36 for the following discussion. w henever the system initially be gins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a tog gle bit is toggling. t ypically, the system w ould note and store the value of the toggle bit after t he first read. after the second read, the system would compare th e new value of the toggle bit with the previous value. if the toggle b it is not toggling, the device h as completed the program or er ases operation. t he system can re ad array data on dq15-dq0 on the following read cycle. however, if after th e initial two read cycles, the system deter mines that the toggle bit is s till toggling, the system also sh ould note whether the value o f dq5 is high (see dq5: exceeded timing limits onpage38 ). if it is, the system sho uld then det ermine again whether the toggle bit is toggling, since the toggle bit may ha ve stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successf ully completed the program or erase operation. if i t is still toggling, t he device did not co mplete the operation successful ly, and the system must write the reset com mand to return to reading array data. the remaining scenario is that t he system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successi ve read cycles, determining the status as described in the prev ious paragraph. alternati vely, it may choose to perform other system tasks. in this case, the system must star t at the beginning of the algorithm when it returns to det ermine the status of the operat ion (top of figure 5.6 on page 37 ). figure 5.6 toggle bit program notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. start read dq7 -dq0 (note 1) erase/program operation not complete toggle bit = toggle? yes no dq5 = 1? no yes read dq7 -dq0 twice (notes 1, 2) toggle bit = toggle? yes no erase/program operation complete read dq7 -dq0
document number: 001-98285 rev. *o page 38 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.5.2.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count l imit. under thes e conditions dq 5 produces a 1. this is a failur e condition that indicates the pr ogram or erase cycle was not s uccessfully completed. the system must issue the reset command to return the device to reading array d ata. when a timeout occurs, the software must send a reset command t o clear the timeout bit (dq5) and to return the eac to read arr ay mode. in this case, it is possible that t he flash will continue to communicate busy for up to 2 s after the re set command is sent.
document number: 001-98285 rev. *o page 39 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.5.2.7 dq1: write-to-buffer abort dq1 indicates whether a write-to -buffer operation was aborted. under these conditions dq1 pro duces a 1. the system must issue the write-to-buffer-abort-reset c ommand sequence to return the eac to standby (read mode) and t he status register failed bits are cleared. see write buffer programming on page 24 for more details. notes: 1. dq5 switches to '1' when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 38 for more information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended line. all addresses other than the program suspended line can be read f or valid data. 4. dq1 indicates the write-to-buffer abort status during write-buffer-programming operations. 5. applies only to program operations. table 5.3 data polling status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 00 reading within erasing se ctor 0 toggle 0 1 toggle n/a 0 reading outside erasing sector 0 toggle 0 1 no toggle n/a 0 program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non-program suspended sector data data data data data data 1 erase suspend mode reading within erase suspended sector 1 no to g g l e 0 n/a toggle n/a 1 reading within non-erase suspend sector data data data data data data 1 programming within non-erase suspended sector dq7# toggle 0 n/a n/a n/a 0 write-to- buffer (notes 4 , 5 ) busy state dq7# toggle 0 n/a no toggle 00 exceeded timing limits dq7# toggle 1 n/a n/a 0 0 abort state dq7# toggle 0 n/a n/a 1 0
document number: 001-98285 rev. *o page 40 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.6 error types and clearing procedures there are three types of errors r eported by the embedded operat ion status methods. depending on the error type, the status reported and procedure for cleari ng the error stat us is differe nt. following is the clea ring of error status: ? if an aso was entered b efore the error the device remains enter ed in the aso awaiting aso read or a command write. ? if an erase was suspe nded before the error the device returns t o the erase suspended state awai ting flash array read or a command write. ? otherwise, the device will be in standby state awaiting flash a rray read or a command write. 5.6.1 embedded operation error if an error occurs during an embedded operation (program, erase , blank check, or password unlock) the device (eac) remains bus y. the ry/by# output remains low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. th e device remains busy until the error status is detected by the host system status monitoring and the error status is cleared. during embedded algorithm error status the data p olling status will show the following: ? dq7 is the inversion of the dq7 b it in the last word loaded int o the write buffer or last word o f the password in the case of the password unlock command. dq7 = 0 for an erase or blank chec k failure ? dq6 continues to toggle ? dq5 = 1; failure of the embedded operation ? dq4 is rfu and should be tr eated as dont care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 continues to toggle, independen t of the address used to rea d status ? dq1 = 0; write buffer abort error ? dq0 is rfu and should be tr eated as dont care (masked) during embedded algorithm error status the stat us register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be er ase suspended during the ea erro r ? sr[5] = 1 on erase or blank check error; else = 0 ? sr[4] = 1 on program or passw ord unlock error; else = 0 ? sr[3] = 0; write buffer abort ? sr[2] = 0; program suspended ? sr[1] = 0; protected sector ? sr[0] = x; rfu, treat as dont care (masked) when the embedded algorithm error status is detected, it is nec essary to clear the error status in order to return to normal o peration, with ry/by# high, ready for a new read or command write. the er ror status can be cleared by writing: ? reset command ? status register clear command commands that are accepted duri ng embedded algorithm error stat us are: ? status register read ? reset command ? status register clear command
document number: 001-98285 rev. *o page 41 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.6.2 protection error if an embedded algorithm attempts to change data within a prote cted area (program, or erase of a protected sector or otp area) the device (eac) goes busy for a pe riod of 20 to 100 s then return s to normal operation. during t he busy period the ry/by# output remains low, data polling status c ontinues to be overlaid on al l address locations, and the stat us register shows not ready wi th invalid status bits (sr[7] = 0). during the protection error sta tus busy period the data polling status will show the following: ? dq7 is the inversion of the dq7 b it in the last word loaded int o the write buffer. dq7 = 0 for an e rase failure ? dq6 continues to toggle, independen t of the address used to rea d status ? dq5 = 0; to indicate no failure of the embedded operation durin g the busy period ? dq4 is rfu and should be tr eated as dont care (masked) ? dq3 = 1 to indicate embedded sector erase in progress ? dq2 continues to toggle, independen t of the address used to rea d status ? dq1 = 0; write buffer abort error ? dq0 is rfu and should be tr eated as dont care (masked) commands that are accepted duri ng the protection error status b usy period are: ? status register read when the busy period ends the device returns to normal operatio n, the data polling status is no longer overlaid, ry/by# is hig h, and the status register sh ows ready with valid status bits. the dev ice is ready for flash array r ead or write of a new command. after the protection error status busy period the status regist er will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be er ase suspended after the protecti on error busy period ? sr[5] = 1 on erase error, else = 0 ? sr[4] = 1 on program error, else = 0 ? sr[3] = 0; program not aborted ? sr[2] = 0; no program in suspension ? sr[1] = 1; error due t o attempting to change a protected locati on ? sr[0] = x; rfu, treat as dont care (masked) commands that are accepted after the protection error status bu sy period are: ? any command
document number: 001-98285 rev. *o page 42 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.6.3 write buffer abort if an error occurs during a writ e to buffer command the device (eac) remains busy. t he ry/by# output remains low, data polling status continues to be overlai d on all address locations, and t he status register shows ready with valid status bits. the devi ce remains busy until the error st atus is detected by the host sys tem status monitoring and the error status is cleared. during write to buffer abort (wba ) error status the data pollin g status will show the following: ? dq7 is the inversion of the dq7 b it in the last word loaded int o the write buffer ? dq6 continues to toggle, independen t of the address used to rea d status ? dq5 = 0; to indicate no failure of the programming operation. w ba is an error in the values i nput by the write to buffer command before the progra mming operation can begin ? dq4 is rfu and should be tr eated as dont care (masked) ? dq3 is don't care after program operation as no erase is in pro gress. if the write buffer program operation was started after an erase operation had been suspended then dq3 = 1. if there wa s no erase operation in progress then dq3 is a don't care and should be masked. ? dq2 does not toggle after program operation as no erase is in p rogress. if the write buffer p rogram operation was started after an erase operation had been suspended then dq2 will toggl e in the sector where the er ase operation was suspended and not in any other sector. if there was no erase operation in progress then dq2 is a don 't care and should be masked. ? dq1 = 1: write buffer abort error ? dq0 is rfu and should be tr eated as dont care (masked) during embedded algorithm error status the stat us register will show the following: ? sr[7] = 1; valid status displayed ? sr[6] = x; may or may not be er ase suspended during the wba err or status ? sr[5] = 0; erase successful ? sr[4] = 1; programming related error ? sr[3] = 1; write buffer abort ? sr[2] = 0; no program in suspension ? sr[1] = 0; sector not l ocked during operation ? sr[0] = x; rfu, treat as dont care (masked) when the wba error status is detec ted, it is nece ssary to clear the error status in order to re turn to normal operation, with ry/by# high, ready for a new read or co mmand write. the error status c an be cleared and device returned to normal operation by writin g: ? write buffer abort reset command Cclears the status r egister and returns to normal operation ? status register clear command commands that are accepted duri ng embedded algorithm error stat us are: ? status register read ? write buffer abort reset command ? status register clear command
document number: 001-98285 rev. *o page 43 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.7 embedded algorithm performance table notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. under worst case conditions of 90c, v cc = 2.70v, 100,000 cycles, and a random data pattern. 4. effective write buffer specification is ba sed upon a 512-byte write buffer operation. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to exec ute the bus-cycle sequence for the program command. see table 7.1, command definitions on page 55 for further information on command definitions. table 5.4 embedded algorithm characteristics (-40c to +85c) parameter typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 275 1100 ms includes pre-programming prior to erasure (note 5) single word programming time (note 1) 125 400 s buffer programming time 2-byte (note 1) 125 750 s 32-byte (note 1) 160 750 64-byte (note 1) 175 750 128-byte (note 1) 198 750 256-byte (note 1) 239 750 512-byte 340 750 effective write buffer program operation per word 512-byte 1.33 s sector programming time 128 kb (full buffer programming) 108 192 ms (note 6) erase suspend/erase resume (t esl ) 40 s program suspend/program resume (t psl ) 40 s erase resume to next erase suspend (t ers )100 s minimum of 60 ns but ? typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs )100 s minimum of 60 ns but ? typical periods are needed for program to progress to completion. blank check 6.2 8.5 ms nop (number of program-operations, per line) 256
document number: 001-98285 rev. *o page 44 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 10,000 cycle, and a random data pattern. 3. under worst case conditions of 105c, v cc = 2.70v, 100,000 cycles, and a random data pattern. 4. effective write buffer specification is ba sed upon a 512-byte write buffer operation. 5. in the pre-programming step of the embedded erase algorithm, all words are programmed to 0000h before sector and chip erasure . 6. system-level overhead is the time required to exec ute the bus-cycle sequence for the program command. see table 7.1, command definitions on page 55 for further information on command definitions. table 5.5 embedded algorithm characteristics (-40c to +105c) parameter typ (note 2) max (note 3) unit comments sector erase time 128 kbyte 275 1100 ms includes pre-programming prior to erasure (note 5) single word programming time (note 1) 125 400 s buffer programming time 2-byte (note 1) 150 1050 s 32-byte (note 1) 200 1050 64-byte (note 1) 220 1050 128-byte (note 1) 250 1050 256-byte (note 1) 320 1050 512-byte 420 1050 effective write buffer program operation per word 512-byte 1.64 s sector programming time 128 kb (full buffer programming) 108 269 ms (note 6) erase suspend/erase resume (t esl ) 50 s program suspend/program resume (t psl ) 50 s erase resume to next erase suspend (t ers )100 s minimum of 60 ns but ? typical periods are needed for erase to progress to completion. program resume to next program suspend (t prs )100 s minimum of 60 ns but ? typical periods are needed for program to progress to completion. blank check 7.6 9.0 ms nop (number of program-operat ions, per line) 1 per 16 word
document number: 001-98285 rev. *o page 45 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 5.7.1 command state transitions notes: 1. state will automatically move to read st ate at the completion of the operation. 2. also known as erase suspend/program suspend legacy method. table 5.6 read command state transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 blank check cfi entry address ra xh x555h x555h x555h (sa)555h (sa)55h data rd xf0h x70h x71h xaah x33h x98h read - read read readsr (read) read readul1 - cfi read protect = false blck readsr - (return) - - - - - - table 5.7 read unlock command state transition current state command and condition read status register read enter unlock 2 word program entry write to buffer enter erase enter id (auto- select) entry ssr entry lock register entry password aso entry ppb entry ppb lock entry dyb aso entry address ra x555h x2aah x555h (sa)xh x555h (sa)555 h (sa)555 h x555h x555h x555h x555h x555h data rd x70h x55h xa0h x25h x80h x90h x88h x40h x60h xc0h x50h xe0h readul1 - readu l1 readsr (read) readu l2 - - - - - - - --- readul2 read protect = true readu l2 readsr (read) - --- cfi -- pp - -- read protect = false pg1 wb er ssr lr ppbl b dyb read protect = false and lr(8) = 0 ppb table 5.8 erase state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 unlock 2 chip erase start sector erase start erase suspend enhanced method (2) address ra xh x555h x555h x555h x2aah x555h (sa)xh xh data rd xf0h x70h x71h xaah x55h x10h x30h xb0h er - er - readsr (read) - erul1 - - - - erul1 - erul1 - readsr (read) --erul2-- - erul2 - erul2 - readsr (read) ---cerser- cer (1) -cer- ersr (cer) ----- - ser (1) sr(7) = 0 ser - ersr (ser) - - - - - esr (es) sr(7) = 1 read read blck (1) sr(7) = 0 blck - ersr (blck) - ---- - sr(7) = 1 read read ersr - (return)
document number: 001-98285 rev. *o page 46 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. state will automatically mo ve to es state by t esl . note: 1. also known as erase resume/program resume legacy method. table 5.9 erase suspend state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 sector erase start address ra xh x555h x555h x555h (sa)xh data rd xf0h x70h x71h xaah x30h esr (1) - esr ersr (esr) - - - es sr(7) = 0 es es essr (es) es esul1 - sr(7) = 1 ser essr - (return) - - - - - table 5.10 erase suspend unlock state command transition current state command and condition read software reset / aso exit status register read enter unlock 1 word progra m entry write to buffer enter write- to- buffer- abort reset start erase resume enhance d method (1) dyb aso entry not a valid write-to-buffer- abort reset command address ra xh x555h x2aah x555h (sa)xh x555h xh x555h not x555h xh not x2aah xh data rd xf0h x70h x55h xa0h x25h xf0h x30h xe0h xh not xf0h xh not x55h esul1 - esul1 - essr (es) esul2 - - - - - - - -- sr(3) = 1 espg espg dq(1) = 1 esul2 - esul2 es essr (es) - espg1 es_w b - ser - -- -- read protect = false esdyb sr(3) = 1 - es - espg espg dq(1) = 1 table 5.11 erase suspend - dyb st ate command t ransition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit dyb set/ clear entry password word count address ra xh x555h x555h xh xh xh xh data rd xf0h x70h x71h x90h x00h xa0h x03h esdyb - esdyb es essr (esdyb) esdyb esdybext - esdybse t - esdybset - esdybset - - - - - - - esdybext - esdybext - - - - es - es
document number: 001-98285 rev. *o page 47 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. also known as erase suspend/program suspend legacy method. notes: 1. state will automatically mo ve to esps state by t psl . 2. also known as erase resume/program resume legacy method. table 5.12 erase suspend - program command state transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 erase suspend enhanced method (1) programsuspend enhanced method write data address ra xh x555h x555h x555h xh xh xh data rd xf0h x70h x71h xaah xb0h x51h xh es_wb wc > 256 or sa ? sa es_wb - - - - - - espg wc ? 256 and sa = sa es_wb_d es_wb_d wc < 0 or write buffer ? write buffer es_wb_d - - - - - - espg wc > 0 and write buffer = write buffer es_wb_d espg1 - espg1 - - - - - - espg espg sr(7) = 0 espg - espgsr (espg) -- espsr (espg) espsr (espg) espg sr(7) = 1 es es esul1 espgsr - (return) - - - - - - (return) table 5.13 erase suspend - program susp end command stat e transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 unlock 2 erase resume enhanced method (2) program resume enhanced method address ra xh x555h x555h x555h x2aah xh xh data rd xf0h x70h x71h xaah x55h x30h x50h espsr (1) - espsr - espgsr (espsr) ----- esps - esps esps espssr (essp) esps espsul1 - espg espg espssr - (return) - - - - - - - espsul1 - espsul1 - espssr (esps) - - espsul2 - - espsul2 - espsul2 - espssr (esps) - - - espg espg table 5.14 program state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 program buffer to flash (confirm) erase suspend enhanced method (2) program suspend enhanced method write data address ra xh x555h x555h x555h (sa)xh xh xh xh data rd xf0h x70h x71h xaah x29h xb0h x51h xh
document number: 001-98285 rev. *o page 48 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s notes: 1. state will automatically move to read st ate at the completion of the operation. 2. also known as erase suspend/program suspend legacy method. notes: 1. state will automatically mo ve to ps state by t psl . 2. also known as erase resume/program resume legacy method. wb wc > 256 or sa ? sa wb------- pg wc ? 256 and sa = sa wb_d wb_d write buffer ? write buffer wb_d------- pg wc = 0 pbf wc > 0 and write buffer = write buffer wb_d pbf- -----pg-- pg pg1-pg1------- pg pg (1) sr(7) = 0 pg - pgsr (pg) -- - psr (pg) psr (pg) pg sr(7) = 1 read read wbul1 - - sr(7) = 1 and sr(1) = 0 table 5.15 program unlock state command transition current state command and condition read software reset / aso exit status register read enter unlock 2 not a valid write-to-buffer-abort reset command address ra xh x555h x2aah not x555h xh not x2aah xh data rd xf0h x70h x55h xh not xf0h xh not x55h wbul1 - wbul1 - - wbul2 - - -- sr(3) = 1 pg pg dq(1) = 1 wbul2 - wbul2 read - - -- -- sr(3) = 1 pg pg dq(1) = 1 pgsr-(return)------- table 5.16 program suspend state command transition current state command and condition read status register read enter status register clear erase resume enhanced method (2) program resume enhanced method address ra x555h x555h xh xh data rd x70h x71h x30h x50h psr (1) - psr pgsr (psr) - - - ps - ps pssr (ps) ps pg pg pssr - (return) - - - - table 5.14 program state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 program buffer to flash (confirm) erase suspend enhanced method (2) program suspend enhanced method write data
document number: 001-98285 rev. *o page 49 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 5.17 lock register state command transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit ppb lock bit set entry password word count address ra xh x555h x555h xh xh xh xh data rd xf0h x70h x71h x90h x00h xa0h x03h lr - lr read lrsr (lr) lr lrext - lrpg1 - lrpg1-lrpg1------- lrpg - lrpg - lrsr (lrpg) - - - - - lrsr-(return)------- lrext - lrext - - - - read - read table 5.18 cfi state command transition current state command and condition read software reset / aso exit status register read enter status register clear address ra xh x555h x555h data rd xf0h x70h x71h cfi - cfi read cfisr (cfi) cfi cfisr - (return) - - - table 5.19 secure silicon sector state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 address ra xh x555h x555h x555h data rd xf0h x70h x71h xaah ssr - ssr read ssrsr (ssr) ssr ssrul1 table 5.20 secure silicon sector unlo ck state command transition current state command and condition read software reset / aso exit status register read enter unlock 2 word program entry write to buffer enter comman d set exit entry not a valid write-to-buffer-abort reset command address ra xh x555h x2aah x555h (sa)xh x555h not x555h xh not x2aah xh data rd xf0h x70h x55h xa0h x25h x90h xh not xf0h xh not x55h ssrul1 - ssrul1 read ssrsr (ssr) ssrul2----- -- dq(1) = 1 ssrpg ssrpg sr(3) = 1 ssrul2 - ssrul2 ssr - - ssrpg1 ssr_wb ssrext -- -- dq(1) = 1 ssrpg ssrpg sr(3) = 1
document number: 001-98285 rev. *o page 50 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 5.21 secure silicon sector program state command transition current state command and condition read software reset / aso exit status register read enter status register clear unlock 1 command set exit address ra xh x555h x555h x555h xh data rd xf0h x70h x71h xaah x00h ssrpg1 - ssrpg1 - - ssrpg1 - - ssr_wb wc > 256 or sa ? sa ssr_wb----- wc ? 256 and sa = sa ssr_wb_d wc < 0 or write buffer ? write buffer ssr_wb_d----- wc > 0 and write buffer = write buffer ssrpg sr(7) = 0 ssrpg - ssrsr (ssrpg) - - - sr(7) = 1 ssr sr(7) = 1 and dq(1) = 0 read dq(1) = 1 - - ssrul1 sr(3) = 1 ssrsr - (return) - - - - - ssrext - ssrext - ssrsr (ssr) - - read table 5.22 password protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear password aso unlock enter password aso unlock start command set exit entry command set exit program entry password word count address ra xh x555h x555h 0h 0h xh xh xh xh data rd xf0h x70h x71h x25h x29h x90h x00h xa0h x03h pp - pp read ppsr (pp) pp ppwb25 - ppext - pppg1 - ppwb25-ppwb25--------ppd ppd wc > 0 ppd ---- - ---- wc ? 0 - pppg pppg1-pppg1--------- pppg - pppg - ppsr (pppg) ------- ppsr-(return)--------- ppext-ppext------read--
document number: 001-98285 rev. *o page 51 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 5.23 non-volatile protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry dyb set start all ppb erase enter all ppb erase start address ra xh x555h x555h xh xh xh (sa)xh xh 0h data rd xf0h x70h x71h x90h x00h xa0h x00h x80h x30h ppb - ppb read ppbsr (ppb) ppb ppbext - ppbpg1 - ppbpg1 - ppbpg1 - ppbpg1 read - - - ppbpg - ppb - ppber ppbpg sr(7) = 0 ppbpg - ppbsr (ppbpg) - ------ sr(7) = 1 read read ppber sr(7) = 0 ppber - ppbsr (ppber) - ------ sr(7) = 1 read read ppbsr-(return)--------- ppbext - ppbext ----read---- table 5.24 ppb lock bit command s tate transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry address ra xh x555h x555h xh xh xh data rd xf0h x70h x71h x90h x00h xa0h ppblb - ppblb read ppblbsr (ppblb) ppblb ppblbext - ppblbset ppblbsr-(return)------ ppblbset - ppblbset----ppblb- lr(2) = 0 and lr(5) = 0 ppblbext - ppblbext ----read- table 5.25 volatile sector protection command state transition current state command and condition read software reset / aso exit status register read enter status register clear command set exit entry command set exit program entry dyb set start dyb clear start address ra xh x555h x555h xh xh xh (sa)xh (sa)xh data rd xf0h x70h x71h x90h x00h xa0h x00h x01h dyb - dyb read dybsr (dyb) dyb dtbext - dybset - - dybsr-(return)-------- dybset-dybset------dybdyb dybext-dybext----read---
document number: 001-98285 rev. *o page 52 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 5.26 state transition definitions current state command transition definition blck table 5.8 blank check cer table 5.8 chip erase start cfi table 5.18 id (autoselect) cfisr table 5.18 id (autoselect) - status register read dyb table 5.25 dyb aso dybext table 5.25 dyb aso - command exit dybset table 5.25 dyb aso - set dybsr table 5.25 dyb aso - status register read er table 5.8 erase enter ersr table 5.8 erase - status register read erul1 table 5.8 erase - unlock cycle 1 erul2 table 5.8 erase - unlock cycle 2 es table 5.9 erase suspended esdyb table 5.11 erase suspended - dyb aso esdybext table 5.11 erase suspended - dyb command exit esdybset table 5.11 erase suspended - dyb set/clear espg table 5.12 erase suspended - program espgsr table 5.12 erase suspended - program - status register read espg1 table 5.12 erase suspended - word program esps table 5.13 erase suspended - program suspended espsr table 5.13 erase suspended - program suspend espssr table 5.13 erase suspended - program su spend - status register read espsul1 table 5.13 erase suspended - program suspend - unlock 1 espsul2 table 5.13 erase suspended - program suspend - unlock 2 esr table 5.9 erase suspend request essr table 5.9 erase suspended - status register read esul1 table 5.10 erase suspended - unlock cycle 1 esul2 table 5.10 erase suspended - unlock cycle 2 es_wb table 5.12 erase suspended - write to buffer es_wb_d table 5.12 erase suspended - write to buffer data lr table 5.17 lock register lrext table 5.17 lock register - command exit lrpg table 5.17 lock register - program lrpg1 table 5.17 lock register - program start lrsr table 5.17 lock register - status register read pbf table 5.14 page buffer full pg table 5.14 program pgsr table 5.15 program - status register read pg1 table 5.14 word program
document number: 001-98285 rev. *o page 53 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s pp table 5.22 password aso ppb table 5.23 ppb ppber table 5.23 ppb - erase ppbext table 5.23 ppb - command exit ppblb table 5.24 ppb lock bit ppblbext table 5.24 ppb lock bit - command exit ppblbset table 5.24 ppb lock bit - set ppblbsr table 5.24 ppb lock bit - stat us register read ppbpg table 5.23 ppb - program ppbpg1 table 5.23 ppb - program request ppbsr table 5.23 ppb - status register read ppd table 5.22 password aso - data ppext table 5.22 password aso - command exit pppg table 5.22 password aso - program pppg1 table 5.22 password aso - program request ppsr table 5.22 password aso - status register read ps table 5.16 program suspended psr table 5.16 program suspend request pssr table 5.16 program suspended - status register read ppwb25 table 5.22 password aso - unlock read table 5.6 read array readsr table 5.6 read status register readul1 table 5.7 read - unlock cycle 1 readul2 table 5.7 read - unlock cycle 2 ser table 5.8 sector erase start ssr table 5.19 secure silicon ssrext table 5.21 secure silicon - command exit ssrpg table 5.21 secure silicon - program ssrpg1 table 5.21 secure silicon - word program ssrsr table 5.21 secure silicon - status register read ssrul1 table 5.20 secure silicon - unlock cycle 1 ssrul2 table 5.20 secure silicon - unlock cycle 2 ssrwb table 5.21 secure silicon - write to buffer ssrwbd table 5.21 secure silicon - write to buffer - write data wb table 5.14 write to buffer wbul1 table 5.15 write buffer - unlock cycle 1 wbul2 table 5.15 write buffer - unlock cycle 2 wbd table 5.14 write to buffer write data table 5.26 state transition definitions (continued) current state command transition definition
document number: 001-98285 rev. *o page 54 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 6. data integrity 6.1 erase endurance note: 1. each write command to a non-volatile register causes a p/e cycl e on the entire non-volatile register array. otp bits and regi sters internally reside in a separate array that is not p/e cycled. 6.2 data retention contact cypress sales or an f ae representative for additional i nformation on the data integrity . an application note is availa ble at http://www.cypre ss.com/appnotes. table 6.1 erase endurance parameter minimum unit program/erase cycles per main flash array sectors 100k p/e cycle program/erase cycles p er ppb array or non-v olatile register arr ay 100k p/e cycle table 6.2 data retention parameter test conditi ons minimum time unit data retention time 10k program/erase cycles 20 years 100k program/erase cycles 2 years
document number: 001-98285 rev. *o page 55 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 7. software int erface reference 7.1 command summary table 7.1 command definitions command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset/aso exit (notes 7 , 16 )1xxxf0 status register read 2 555 70 xxx rd status register clear 1 555 71 word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 11) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend legacy method (note 9) 1 xxx b0 erase suspend enhanced method erase resume/program resume legacy method (note 10) 1 xxx 30 erase resume enhanced method program suspend enhanced method 1 xxx 51 program resume enhanced method 1 xxx 50 blank check 1 (sa) 555 33 id-cfi (autoselect) aso id (autoselect) entry 3 555 aa 2aa 55 (sa) 555 90 cfi enter (note 8) 1 (sa) 55 98 id-cfi read 1 ra rd reset/aso exit (notes 7 , 16 ) 1 xxx f0 secure silicon region command definitions secure silicon region (ssr) aso ssr entry 3 555 aa 2aa 55 (sa) 555 88 read (note 6) 1 ra rd word program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 6 555 aa 2aa 55 sa 25 sa wc wbl pd wbl pd program buffer to flash (confirm) 1sa29 write-to-buffer-abort reset (note 11) 3 555 aa 2aa 55 555 f0 ssr exit (note 11) 4 555 aa 2aa 55 555 90 xx 0 reset/aso exit (notes 7 , 16 ) 1 xxx f0
document number: 001-98285 rev. *o page 56 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s lock register command set definitions lock register aso lock register entry 3 555 aa 2aa 55 555 40 program (note 15) 2 xxx a0 xxx pd read (note 15) 1 0 rd command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 16 ) 1 xxx f0 password protection command set definitions password aso password aso entry 3 555 aa 2aa 55 555 60 program (note 14) 2 xxx a0 pwa x pwdx read (note 13) 4 0 pwd0 1 pwd1 2 pwd2 3 p w d 3 unlock 7 0 25 0 3 0 pwd0 1 pwd 1 2 pwd2 3 p w d 3 029 command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 16 ) 1 xxx f0 non-volatile sector protection command set definitions ppb (non-volatile sector protection) ppb entry 3 555 aa 2aa 55 555 c0 ppb program (note 17) 2 xxx a0 sa 0 all ppb erase (note 17) 2xxx80030 ppb read (note 17) 1 sa rd (0) command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (notes 7 , 16 ) 1 xxx f0 global non-volatile sector protection freeze command set defini tions ppb lock bit ppb lock entry 3 555 aa 2aa 55 555 50 ppb lock bit cleared 2 xxx a0 xxx 0 ppb lock status read (note 17) 1 xxx rd (0) command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (note 16) 1 xxx f0 table 7.1 command definitions (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 001-98285 rev. *o page 57 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s legend: x = don't care. ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector selected. address bits a max -a16 uniquely select any sector. wbl = write buffer location. the address must be within the same line. wc = word count is the number of write buffer locations to load minus 1. pwax = password address for word0 = 00h, word1 = 01h, word2 = 02h, and word3 = 03h. pwdx = password data word0, word1, word2, and word3. notes: 1. see table 9.1, interface states on page 66 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: r ead cycle during re ad, id/cfi read (manufact uring id / device id), indicator bits, secure silicon region read, ssr lock read, and 2nd cycle of status register read . 4. data bits dq15-dq8 are don't care in command sequences, except for rd, pd, wc and pwd. 5. address bits a max -a11 are don't cares for unlock and command cycles, unless sa or pa required. ( a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the id-cfi (autoselect) mode, or if dq5 goes high (while the device is providing status data). 8. command is valid when device is ready to read array data or when device is in id-cfi (autoselect) mode. 9. the system can read and program/program suspend in non-erasing sectors, or enter the id-cfi aso, when in the erase suspend mo de. the erase suspend command is valid only during a sector erase operation. 10. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 11. issue this command sequence to return to read mode after detec ting device is in a write-to-buffer-abort state. important: th e full command sequence is required if resetting out of abort. 12. the exit command returns the device to reading the array. 13. the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 14. for pwdx, only one portion of the password can be programmed per each a0 command. portions of the password must be programme d in sequential order (pwd0 - pwd3). 15. all lock register bits are one-time programmable. the program state = 0 and the erase state = 1. also, both the persistent p rotection mode lock bit and the password protection mode lock bit cannot be progr ammed at the same time or the lock register bits program oper ation aborts and returns the device to read mode. lock register bits that are reserved for future use are undefined and may be 0?s or 1's. 16. if any of the entry commands was issued, an exit comm and must be issued to reset the device into read mode. 17. protected state = 00h, unprotected state = 01h. the sector address for dyb set, dyb clear, or ppb program command may be any location within the sector - the lower order bits of the sector address are don't care. volatile sector protecti on command set definitions dyb (volatile sector protection) aso dyb aso entry 3 555 aa 2aa 55 555 e0 dyb set (note 17) 2 xxx a0 sa 0 dyb clear (note 17) 2 xxx a0 sa 1 dyb status read (note 17) 1 sa rd (0) command set exit (notes 12 , 16 ) 2 xxx 90 xxx 0 reset/aso exit (note 16) 1 xxx f0 command set definitions ecc ecc aso ecc aso entry 3 555 aa 2aa 55 555 75 ecc status read 1 ra rd command set exit (notes 12 , 16 ) 1xxxf0 table 7.1 command definitions (continued) command sequence (note 1) cycles bus cycles (notes 2 - 5 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
document number: 001-98285 rev. *o page 58 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 7.2 device id and common flash interface (id-cfi) aso map the device id portion of the aso (word locations 0h to 0fh) pro vides manufacturer id, device id, sector protection state, and basic feature set informati on for the device. id-cfi location 02h displays sect or protection status for the s ector selected b y the sector address (sa) used in the id-cfi en ter command. to read the protection s tatus of more than one sector it is necessary to exit the id aso and enter the id aso using t he new sa. the access time to read location 02h is always t acc and a read of this location requires ce# to go high before the read and return low to initiate the re ad (asynchronous read access). pag e mode read between loc ation 02h and other id locations is not supported. page mode read between id locations other than 02h i s supported. for additional information see id-cfi aso on page 31 . table 7.2 id (autoselect) address map description address read data manufacture id (sa) + 0000h 0001h device id (sa) + 0001h 227eh protection verification (sa) + 0002h sector protection state (1= sect or protected, 0= sector unprote cted). this protection state is shown only for the sa se lected when enter ing id-cfi as o. reading other sa provides undefined data. to read a different sa protection stat e aso exit command must be used and then enter id -cfi aso again with the new sa. indicator bits (sa) + 0003h dq15-dq08 = 1 (reserved) dq7 - factory locked se cure silicon region 1 = locked, 0 = not locked dq6 - customer locked secure silicon region 1 = locked 0 = not locked dq5 = 1 (reserved) dq4 - wp# protects 0 = lowest address sector 1 = highest address sector dq3 - dq0 = 1 (reserved) rfu (sa) + 0004h reserved (sa) + 0005h reserved (sa) + 0006h reserved (sa) + 0007h reserved (sa) + 0008h reserved (sa) + 0009h reserved (sa) + 000ah reserved (sa) + 000bh reserved
document number: 001-98285 rev. *o page 59 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s lower software bits (sa) + 000ch bit 0 - status register support 1 = status register supported 0 = status register not supported bit 1 - dq polling support 1 = dq bits polling supported 0 = dq bits polling not supported bit 3-2 - command set support 11 = reserved 10 = reserved 01 = reduced command set 00 = classic command set bits 4-15 - reserved = 0 upper software bits (sa) + 000dh reserved device id (sa) + 000eh 2228h = 1 gb 2223h = 512 mb 2222h = 256 mb 2221h = 128 mb device id (sa) + 000fh 2201h table 7.3 cfi query identification string word address data description (sa) + 0010h (sa) + 0011h (sa) + 0012h 0051h 0052h 0059h query unique ascii string qry (sa) + 0013h (sa) + 0014h 0002h 0000h primary oem command set (sa) + 0015h (sa) + 0016h 0040h 0000h address for primary extended table (sa) + 0017h (sa) + 0018h 0000h 0000h alternate oem command set (00h = none exists) (sa) + 0019h (sa) + 001ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 7.2 id (autoselect) address map (continued) description address read data
document number: 001-98285 rev. *o page 60 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s table 7.4 cfi system interface string word address data description (sa) + 001bh 0027h v cc min. (erase/program) (d7-d4 : volts, d3-d0: 100 mv) (sa) + 001ch 0036h v cc max. (erase/program) (d7-d4: volts, d3-d0: 100 mv) (sa) + 001dh 0000h v pp min. voltage (00h = no v pp pin present) (sa) + 001eh 0000h v pp max. voltag e (00h = no v pp pin present) (sa) + 001fh 0008h typical timeout per single word write 2 n s (sa) + 0020h 0009h typical timeout for max multi-byte program, 2 n s (00h = not supported) (sa) + 0021h 0008h typical timeout per individual block erase 2 n ms (sa) + 0022h 0012h (1 gb) 0011h (512 mb) 0010h (256 mb) 000fh (128 mb) typical timeout for full chip erase 2 n ms (00h = not supported) (sa) + 0023h 0001h max. timeout for single word write 2 n times typical (sa) + 0024h 0002h max. time out for buffer write 2 n times typical (sa) + 0025h 0003h max. timeout p er individual block erase 2 n times typical (sa) + 0026h 0003h max. timeout for full chip erase 2 n times typical (00h = not supported) table 7.5 cfi device geometry definition word address data description (sa) + 0027h 001bh (1 gb) 001ah (512 mb) 0019h (256 mb) 0018h (128 mb) device size = 2 n byte; (sa) + 0028h 0001h flash device interface descripti on 0 = x8-only, 1 = x16-only, 2 = x8/x16 capable (sa) + 0029h 0000h (sa) + 002ah 0009h max. number of byte in multi-byte write = 2 n (00 = not supported) (sa) + 002bh 0000h (sa) + 002ch 0001h number of erase block regions within device 1 = uniform device, 2 = boot device (sa) + 002dh 00xxh erase block region 1 information (refer to jed ec jesd68-01 or jep137 specifications) 00ffh, 0003h, 0000h, 0002h =1 gb 00ffh, 0001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 00 00h, 0002h = 128 mb (sa) + 002eh 000xh (sa) + 002fh 0000h (sa) + 0030h 000xh (sa) + 0031h 0000h erase block region 2 information (refer to cfi publication 100) (sa) + 0032h 0000h (sa) + 0033h 0000h (sa) + 0034h 0000h
document number: 001-98285 rev. *o page 61 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s (sa) + 0035h 0000h erase block region 3 information (refer to cfi publication 100) (sa) + 0036h 0000h (sa) + 0037h 0000h (sa) + 0038h 0000h (sa) + 0039h 0000h erase block region 4 information (refer to cfi publication 100) (sa) + 003ah 0000h (sa) + 003bh 0000h (sa) + 003ch 0000h (sa) + 003dh ffffh reserved (sa) + 003eh ffffh reserved (sa) + 003fh ffffh reserved table 7.6 cfi primary vendor-specific extended query word address data description (sa) + 0040h 0050h query-unique ascii string pri (sa) + 0041h 0052h (sa) + 0042h 0049h (sa) + 0043h 0031h major version number, ascii (sa) + 0044h 0035h minor version number, ascii (sa) + 0045h 001ch address sensitive unlock (bits 1-0) 00b = required 01b = not required process technology (bits 5-2) 0000b = 0.23 m floating gate 0001b = 0.17 m floating gate 0010b = 0.23 m mirrorbit 0011b = 0.13 m floating gate 0100b = 0.11 m mirrorbit 0101b = 0.09 m mirrorbit 0110b = 0.09 m floating gate 0111b = 0.065 m mirrorbit eclipse 1000b = 0.065 m mirrorbit 1001b = 0.045 m mirrorbit (sa) + 0046h 0002h erase suspend 0 = not supported 1 = read only 2 = read and write (sa) + 0047h 0001h sector protect 00 = not supported x = number of sector s in smallest group (sa) + 0048h 0000h temporary sector unprotect 00 = not supported 01 = supported table 7.5 cfi device geometry definition (continued) word address data description
document number: 001-98285 rev. *o page 62 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s (sa) + 0049h 0008h sector protect/u nprotect scheme 04 = high voltage method 05 = software command locking method 08 = advanced secto r protection method (sa) + 004ah 0000h simultaneous operation 00 = not supported x = number of banks (sa) + 004bh 0000h burst mode type 00 = not supported 01 = supported (sa) + 004ch 0003h page mode type 00 = not supported 01 = 4 word page 02 = 8 word page 03=16 word page (sa) + 004dh 0000h acc (acceleration) supply minimum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004eh 0000h acc (acceleration) supply maximum 00 = not supported d7-d4: volt d3-d0: 100 mv (sa) + 004fh 0004h (bottom) 0005h (top) wp# protection 00h = flash devi ce without wp protect (no boot) 01h = eight 8 kb sectors at top and bottom with wp (dual boot) 02h = bottom boot device wi th wp protect (bottom boot) 03h = top boot device wi th wp protect (top boot) 04h = uniform, bottom wp pro tect (uniform bottom boot) 05h = uniform, top wp pro tect (uniform top boot) 06h = wp protect for all sectors 07h = uniform, top and bottom wp protect (sa) + 0050h 0001h program suspend 00 = not supported 01 = supported (sa) +0051h 0000h unlock bypass 00 = not supported 01 = supported (sa) + 0052h 0009h secured silicon sector (customer otp area) siz e 2 n (bytes) (sa) + 0053h 008fh software features bit 0: status register polling (1 = supported, 0 = not supporte d) bit 1: dq polling (1 = suppo rted, 0 = not supported) bit 2: new program suspend/resume commands (1 = supported, 0 = n o t s u p p o r t e d ) bit 3: word programming (1 = s upported, 0 = n ot supported) bit 4: bit-field programming (1 = supported, 0 = not supported) bit 5: autodetect prog ramming (1 = supporte d, 0 = not supported ) bit 6: rfu bit 7: multiple writes per line (1 = supported, 0 = not support ed) table 7.6 cfi primary vendor-specific extended query (continued) word address data description
document number: 001-98285 rev. *o page 63 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 7.3 device id and common flash interface (id-cfi) aso map (sa) + 0054h 0005h page size = 2 n bytes (sa) + 0055h 0006h erase susp end timeout maximum < 2 n (s) (sa) + 0056h 0006h program suspend timeout maximum < 2 n (s) (sa) + 0057h to (sa) + 0077h ffffh reserved (sa) + 0078h 0006h embedded hardware reset timeout maximum < 2 n (s) reset with reset pin (sa) + 0079h 0009h non-embedded hardware res et timeout maximum < 2 n (s) power on reset table 7.7 device id and common flash in terface (id-cfi) aso map word address data field # of bytes data format example of actual data hex read out of example data (sa) + 0080h size of electronic marking 1 hex 19 0013h (sa) + 0081h revision of electronic marking 1 hex 1 0001h (sa) + 0082h fab lot # 7 ascii ld87270 004ch, 0044h,0038h, 0037h,0032h, 0037h, 0030h (sa) + 0089h wafer # 1 hex 23 0017h (sa) + 008ah die x coordinate 1 hex 10 000ah (sa) + 008bh die y coordinate 1 hex 15 000fh (sa) + 008ch class lot# 7 ascii br33150 0042h, 0052h, 0033h, 0033h,0031h, 0035h, 0030h (sa) + 0093h reserved for future 13 n/a n/a undefined fab lot # + wafer # + die x coordinate + die y coordinate gives a unique id for each device. table 7.6 cfi primary vendor-specific extended query (continued) word address data description
document number: 001-98285 rev. *o page 64 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s hardware interface 8. signal descriptions 8.1 address and data configuration address and data are co nnected in parallel (adp) via separate s ignal inputs and i/os. 8.2 input/output summary table 8.1 i/o summary symbol type description reset# input hardware reset. at v il , causes the device to reset control logic to its standby state , ready for reading array data. ce# input chip enable. at v il , selects the device for data transfer with the host memory controller. oe# input output enable. at v il , causes outputs to be actively driven. at v ih , causes outputs to be high impedance (high-z). we# input write enable. at v il , indicates data transfer from host to device. at v ih , indicates data transfer is from device to host. a max -a0 input address inputs. a25-a0 for s29gl01gs a24-a0 for s29gl512s a23-a0 for S29GL256S a22-a0 for s29gl128s dq15-dq0 input/output data inputs and outputs wp# input write protect. at v il , disables program and erase f unctions in the lowest or highest address 64-kword (128-kb) sector of the device. at v ih , the sector is not protected. wp# has an internal pull up; when unconn ected wp# is at v ih . ry/by# output - open drain ready/busy. indicates whether an embedded algorithm is in progr ess or complete. at v il , the device is actively engaged in an embedded algorithm such as erasing or programming. at high-z, the devic e is ready for read or a new c ommand write - requires external pull-up resisto r to detect the high-z state. multiple devices may have their ry/by# outputs tied togeth er to detect when all devices a re ready. v cc power supply core power supply v io power supply versatile io power supply. v ss power supply power supplies ground nc no connect not connected internally. the pin/ball location may be used in printed circuit board (pcb) as part of a routing channel. rfu no connect reserved for future use. not currently connected internally but the pin/ball location should be left unconnected and unused by pcb routing channel fo r future compatibility. the pin/ball may be used by a signal in the futu re. dnu reserved do not use. reserved for use by cypress. the pin/ball is connec ted internally. the input has an internal pull down resistance to v ss . the pin/ball can be left open or tied to v ss on the pcb.
document number: 001-98285 rev. *o page 65 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 8.3 versatile i/o feature the maximum output voltage level d riven by, and input levels ac ceptable to, the device ar e determined by the v io power supply. this supply allows the device to drive and receive signals to a nd from other devices on the same bus having interface signal l evels different from the d evice core voltage. 8.4 ready/busy# (ry/by#) ry/by# is a dedicated, open drain output pin that indicates whe ther an embedded algorithm, power-on reset (por), or hardware reset is in progress or complete. the ry/by# status is valid af ter the rising edge of the final we# pulse in a command sequenc e, when v cc is above v cc minimum during por, or after the falling edge of reset#. since ry/by# is an open drain output, several ry/by# pins can be tied together in parallel with a pull up res istor to v io . if the output is low (busy), the device is actively erasing, pr ogramming, or resettin g. (this includes pro gramming in the eras e suspend mode). if the output is high (ready), the device is rea dy to read data (including durin g the erase suspend mode), or i s in the standby mode. table 5.3, data polling status on page 39 shows the outputs for r y/by# in each operation. if an embedded algorithm has failed (program / erase failure as result of max pulses or sector is locked), ry/by# will stay low ( busy) until status re gister bits 4 and 5 are cleared and the reset command is issued. this includes eras e or programming on a locked sector. 8.5 hardware reset the reset# input provides a har dware method of r esetting the de vice to standby state. when reset# is driven low for at least a period of t rp , the device immediately: ? terminates any operation in progress, ? exits any aso, ? tristates all outputs, ? resets the status register, ? resets the eac to standby state. ? ce# is ignored for the durat ion of the reset operation (t rph ). ? to meet the reset current specification (i cc5 ) ce# must be held high. to ensure data integr ity any operation that was interrupted sho uld be reinitiated once the d evice is ready to accept another command sequence.
document number: 001-98285 rev. *o page 66 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 9. signal protocols the following sections describe the host system interface signa l behavior and timing for the 29gl-s family flash devices. 9.1 interface states table 9.1 describes the required value of each interface signal for each interface state. legend: l = v il h = v ih x = either v il or v ih l/h = rising edge h/l = falling edge valid = all bus signals have stable l or h level modified = valid state different from a previous valid state available = read data is internally stored with output driver controlled by oe# notes: 1. we# and oe# can not be at v il at the same time. 2. read with output disable is a read initiated with oe# high. 3. automatic sleep is a read/write operation where data has been driven on the bus for an extended period, without ce# going hig h and the device internal logic has gone into standby mode to conserve power. 9.2 power-off with hardware data protection the memory is considered to be powered off when the core power supply (v cc ) drops below the lock-out voltage (v lko ). when v cc is below v lko , the entire memory array is pro tected against a program or era se operation. this ensures t hat no spurious alteration of the memory content can occur during power transition. during a power supply transition down to power-off, v io should remain less than or equal to v cc . if v cc goes below v rst (min) then returns above v rst (min) to v cc minimum, the power-on reset in terface state is entered and the eac starts th e cold reset embedded algorithm. table 9.1 interface states interface state v cc v io reset# ce# oe# we# a max -a0 dq15-dq0 power-off with hardware data protection < v lko ? v cc x x x x x high-z power-on (cold) reset ? v cc min ? v io min ? v cc x x x x x high-z hardware (warm) reset ? v cc min ? v io min ? v cc l x x x x high-z interface standby ? v cc min ? v io min ? v cc h h x x x high-z automatic sleep (notes 1 , 3 ) ? v cc min ? v io min ? v cc h l x x valid output available read with output disable (note 2) ? v cc min ? v io min ? v cc h l h h valid high-z random read ? v cc min ? v io min h l l h valid output valid page read ? v cc min ? v io min ? v cc hllh a max -a4 valid a3-a0 modified output valid write ? v cc min ? v io min ? v cc h l h l valid input valid
document number: 001-98285 rev. *o page 67 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 9.3 power conservation modes 9.3.1 interface standby standby is the default, low powe r, state for the interface whil e the device is not selected by the host for data transfer (ce# = high). all inputs are ignored in this state and all outputs except ry/ by# are high impedance. ry/by# is a direct output of the eac, n ot controlled by the host interface. 9.3.2 automatic sleep the automatic sleep mo de reduces device int erface energy consum ption to the sleep level (i cc6 ) following the co mpletion of a random read access time. the devic e automatically enables this mode when addresses re main stable for t acc + 30 ns. while in sleep mode, output data is latched and always available to the system. output of the data depen ds on the level of the oe# sign al but, the automatic sleep mode current is independe nt of the oe# signal level. standard address access timings (t acc or t pacc ) provide new data when addresses are changed. i cc6 in dc characteristics on page 72 represents the automat ic sleep mode current specification. automatic sleep helps reduce cu rrent consumption especially whe n the host system clock is slowed for power reduction. during slow system clock periods, read a nd write cycles may extend man y times their length versus wh en the system is operating at hig h speed. even though ce# may be lo w throughout these extended dat a transfer cycles, the memory dev ice host i nterface will go to the automatic sleep current at t acc + 30 ns. the device will remain at the automatic sleep current for t assb . then the device will transition to the standby current l evel. this keeps the memory at the automatic sleep or standby power level for most of the l ong duration data transfer cycles, r ather than consuming full read power all the time that the memor y device is selected by the ho st system. however, the eac operates inde pendent of the automatic sleep mo de of the host interface and will continue to draw current duri ng an active embedded algorithm. on ly when both the host interface and eac are in their standby st ates is the standby level curre nt achieved. 9.4 read 9.4.1 read with output disable when the ce# signal is asserted low, the host system memory con troller begins a read or write data transfer. often there is a period at the beginning of a data transfer when ce# is low, address is valid, oe# is high, and we# is high. during this state a read access is assumed and the random read process is started while the dat a outputs remain at high impedance. if the oe# signal goes low, the interface transitions to the random read state, with data o utputs actively driven. if the we # signal is asserted low, the interface transitions to the write state. note, oe# and we# should never be low at the same time to ensu re no data bus contention betwee n the host system and memory. 9.4.2 random (as ynchronous) read when the host syst em interface selects the memory device by dri ving ce# low, the device interfa ce leaves the standby state. if we# is high when ce# goes low, a random read access is started. the data output depends on t he address map mode and the address provided at t he time the read access is started. the data appears on dq15-dq0 when ce# is low, oe# is low, we# r emains high, address remains stable, and the asynchronous access times are satisfi ed. address access time (t acc ) is equal to the delay from st able addresses to valid output d ata. the chip enable access time (t ce ) is the delay from stable ce# to valid data at t he outputs. in order for the read data to be driven on to the data outputs the oe# signal must be low at least the output ena ble time (t oe ) before valid data is available. at the completion of the random access time from ce# active (t ce ), address stable (t acc ), or oe# active (t oe ), whichever occurs latest, the data output s will provide valid read data from the currently active address map mode. if ce# remains low and any o f the a max to a4 address signals change to a new value, a new random read access begins. if ce# remains low and oe# goes high the interface transitions to the re ad with output disable state. if ce# remains low, oe# goes high, and we# goes low, the interfac e transitions to the write state. if ce# returns high, the interf ace goes to the standb y state. back to back accesses, in which ce# remains low between accesses, re quires an address change to ini tiate the second access. see asynchronous read operations on page 78 .
document number: 001-98285 rev. *o page 68 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 9.4.3 page read after a random read access is com pleted, if ce# remains low, oe # remains low, the a max to a4 address signal s remain stable, and any of the a3 to a0 address signals change, a new access wi thin the same page begins. th e page read completes much faster (t pacc ) than a random read access. 9.5 write 9.5.1 asynchronous write when we# goes low after ce is low , there is a transition from o ne of the read states to the wri te state. if we# is low before ce# goes low, there is a transition from the standby state directly to the write state without beginning a read access. when ce# is low, oe# is high, a nd we# goes low, a write data tr ansfer begins. note, oe# and w e# should never be low at the same time to ensure no data bu s contention between the host sys tem and memory. when the asynchronous w rite cycle timing requirements are met the we# can go high to capture the address and data values in to eac command memory. address is captured by the falli ng edge of we# or ce#, whicheve r occurs later. data is captured b y the rising edge of we# or c e#, whichever occurs earlier. when ce# is low before we# goes low and stays low after we# goe s high, the access is called a we# cont rolled write. when we# is high and ce# goes high, t here is a transition to the sta ndby state. if ce# remains low and we# goes high, there is a transition to the read with output disable state. when we# is low before ce# goes low and remains low after ce# g oes high, the access is called a ce# controlled write. a ce# controlled write transitions to the standby state. if we# is low before ce# goes low, the write transfer is starte d by ce# going low. if we# is low after ce# goes high, the addr ess and data are captured by the ri sing edge of ce#. these cases ar e referred to as ce# controlled write state transitions. write followed by re ad accesses, in which ce# remains low betwe en accesses, requires an addr ess change to initiate the following read access. back to back accesses, in which ce# remains low between accesse s, requires an address change to initiate the second access. the eac command memory array is not readable by the host system and has no aso. the eac examines the address and data in each write transfer to determine if the write is part of a lega l command sequence. when a legal command sequence is complete t he eac will initiate the appropriate ea. 9.5.2 write pulse glitch protection noise pulses of less than 5 ns ( typical) on we# will not initia te a write cycle. 9.5.3 logical inhibit write cycles are inhibit ed by holding oe# at v il , or ce# at v ih , or we# at v ih . to initiate a write cycle , ce# and we# must be low (v il ) while oe# is high (v ih ).
document number: 001-98285 rev. *o page 69 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 10. electrical specifications 10.1 absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 10.3 on page 71 . maximum dc voltage on input or i/o pins is v cc +0.5v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 10.4 on page 71 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 10.2 latchup characteristics this product complies with jede c standard jesd78c latchup testi ng requirements. 10.3 thermal resistance 10.4 operating ranges 10.4.1 temperature ranges table 10.1 absolute maximum ratings storage temperature plastic packages -65c to +150c ambient temperature with po wer applied -65c to +125c voltage with respect to ground all pins other than reset# (note 1) -0.5v to (v io + 0.5v) reset# (note 1) -0.5v to (v cc + 0.5v) output short circuit current (note 2) 100 ma v cc -0.5v to +4.0v v io -0.5v to +4.0v table 10.2 thermal resistance parameter description laa064 lae064 ts056 unit theta ja thermal resistance (junc tion to ambient) 25 20.4 46.2 c/w parameter symbol device spec unit min max ambient temperature t a industrial (i) C40 +85 c industrial plus (v) C40 +105 automotive, aec-q100 grade 3 (a) C40 +85 automotive, aec-q100 grade 2 (b) C40 +105
document number: 001-98285 rev. *o page 70 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 10.4.2 power supply voltages operating ranges defi ne those limits between which the function ality of the device is guaranteed. 10.4.3 power-up and power-down during power-up or power-down v cc must always be great er than or equal to v io (v cc ? v io ). the device ignores all inpu ts until a time delay of t vcs has elapsed after the moment that v cc and v io both rise above, and stay above, the minimum v cc and v io thresholds. during t vcs the device is performing pow er on reset operations. during power-down or v oltage drops below v cc lockout maximum (v lko ), the v cc and v io voltages must drop below v cc reset (v rst ) minimum for a period of t pd for the part to initial ize correctly when v cc and v io again rise to their operating ranges. see figure 10.2 on page 71 . if during a voltage drop the v cc stays above v lko maximum the part will stay i nitialized and will work correctly when v cc is again above v cc minimum. if the par t locks up from improper initialization, a hardware reset can be used to initialize the p art correctly. normal precautions must be tak en for supply decoupling to stabi lize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a s uitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). at no time should v io be greater then 200 mv above v cc (v cc ? v io - 200 mv). note: 1. not 100% tested. figure 10.1 power-up v cc 2.7v to 3.6v v io 1.65v to v cc + 200 mv table 10.3 power-up/power-down voltage and timing symbol parameter min max unit v cc v cc power supply 2.7 3.6 v v lko v cc level below which re-initialization is required (note 1) 2.25 2.5 v v rst v cc and v io low voltage needed to ensure initialization will occur (note 1) 1.0 v t vcs v cc and v io ? minimum to first access (note 1) 300 s t pd duration of v cc ? v rst (min) (note 1) 15 s vcc (max) vcc (min) power supply voltage tim e t vcs full device access vcc v io (min) v io (max) v io
document number: 001-98285 rev. *o page 71 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 10.2 power-down and voltage drop 10.4.4 input sig nal overshoot figure 10.3 maximum negative overshoot waveform figure 10.4 maximum positive o vershoot waveform v cc (max) v cc (min) v cc and v io tim e v rst (min) t pd t vcs no device access allowed full device access allowed v lko (max) 20 ns 20 n s 20 ns ?2 .0 v v max il v min il 20 ns 20 ns 20 ns v io + 2.0 v v max ih v min ih
document number: 001-98285 rev. *o page 72 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 10.5 dc characteristics notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedde d operation, i cc5 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 10.4 dc characteristics (-40c to +85c) parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max +0.02 1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max +0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (notes 1 , 2 ) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 100 a i cc5 v cc reset current (notes 2 , 7 ) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (note 3) v ih = v io , v il = v ss , v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 150 a i cc7 v cc current during power up (notes 2 , 6 ) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (note 4) -0.5 0.3 x v io v v ih input high voltage (note 4) 0.7 x v io v io + 0.4 v v ol output low voltage (notes 4 , 8 ) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (note 4) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (note 2) 2.25 2.5 v v rst low v cc power on reset voltage (note 2) 1.0 v
document number: 001-98285 rev. *o page 73 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s notes: 1. i cc active while embedded algorithm is in progress. 2. not 100% tested. 3. automatic sleep mode enables the lower power mode when addresses remain stable for the specified designated time. 4. v io = 1.65v to v cc or 2.7v to v cc depending on the model. 5. v cc = 3v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at >1.8v. 6. during power-up there are spikes of current demand, the system needs to be able to supply this current to insure the part ini tializes correctly. 7. if an embedded operation is in progress at the start of reset, the current consumption will remain at the embedded operation specification until the embedded operation is stopped by the reset. if no embedded operation is in progress when reset is started, or following the stopping of an embedde d operation, i cc7 will be drawn during the remainder of t rph . after the end of t rph the device will go to standby mode until the next read or write. 8. the recommended pull-up resistor for ry/by# output is 5k to 10k ohms. table 10.5 dc characteristics (-40c to +105c) parameter description test conditions min typ (note 2) max unit i li input load current v in = v ss to v cc , v cc = v cc max +0.02 1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max +0.02 1.0 a i cc1 v cc active read current ce# = v il , oe# = v ih , address switching@ 5 mhz, v cc = v cc max 55 60 ma i cc2 v cc intra-page read current ce# = v il , oe# = v ih , address switching@ 33 mhz, v cc = v cc max 925ma i cc3 v cc active erase/program current (notes 1 , 2 ) ce# = v il , oe# = v ih , v cc = v cc max 45 100 ma i cc4 v cc standby current ce#, reset#, oe# = v ih , v ih = v io v il = v ss , v cc = v cc max 70 200 a i cc5 v cc reset current (notes 2 , 7 ) ce# = v ih , reset# = v il , v cc = v cc max 10 20 ma i cc6 automatic sleep mode (note 3) v ih = v io , v il = v ss , v cc = v cc max, t acc + 30 ns 36ma v ih = v io , v il = v ss , v cc = v cc max, t assb 100 200 a i cc7 v cc current during power up (notes 2 , 6 ) reset# = v io, ce# = v io , oe# = v io , v cc = v cc max, 53 80 ma v il input low voltage (note 4) -0.5 0.3 x v io v v ih input high voltage (note 4) 0.7 x v io v io + 0.4 v v ol output low voltage (notes 4 , 8 ) i ol = 100 a for dq15-dq0; i ol = 2 ma for ry/by# 0.15 x v io v v oh output high voltage (note 4) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (note 2) 2.25 2.5 v v rst low v cc power on reset voltage (note 2) 1.0 v
document number: 001-98285 rev. *o page 74 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 10.6 capacitance characteristics notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. table 10.6 connector capacitance for fbga (laa) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 8 9 pf c out output capacitance v out = 0 5 7 pf c in2 control pin capacitance v in = 0 4 8 pf ry/by# output capacitance v out = 0 3 4 pf table 10.7 connector capacitance for fbga (lae) package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 7 8 pf c out output capacitance v out = 0 5 6 pf c in2 control pin capacitance v in = 0 3 7 pf ry/by# output capacitance v out = 0 3 4 pf table 10.8 connector capacitance for tsop package parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 7 8 pf c out output capacitance v out = 0 5 6 pf c in2 control pin capacitance v in = 0 3 7 pf ry/by# output capacitance v out = 0 3 4 pf
document number: 001-98285 rev. *o page 75 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 11. timing specifications 11.1 key to switching waveforms 11.2 ac test conditions figure 11.1 test setup note: 1. measured between v il max and v ih min. waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is h igh impedance state (high-z) table 11.1 test specification parameter all speeds units output load capacitance, c l 30 pf input rise and fall times (note 1) 1.5 ns input pulse levels 0.0-v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v c l device under te s t
document number: 001-98285 rev. *o page 76 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.2 input waveforms and measurement levels 11.3 power-on reset (por) and warm reset normal precautions must be tak en for supply decoupling to stabi lize the v cc and v io power supplies. each device in a system should have the v cc and v io power supplies decoupled by a s uitable capacitor close to the package connections (this capacitor is generally on the order of 0.1 f). notes: 1. not 100% tested. 2. timing measured from v cc reaching v cc minimum and v io reaching v io minimum to v ih on reset and v il on ce#. 3. reset# low is optional during por. if reset is asserted during por, the later of t rph , t vios , or t vcs will determine when ce# may go low. if reset# remains low after t vios , or t vcs is satisfied, t rph is measured from the end of t vios , or t vcs . reset must also be high t rh before ce# goes low. 4. v cc ? v io - 200 mv during power-up. 5. v cc and v io ramp rate can be non-linear. 6. sum of t rp and t rh must be equal to or greater than t rph. 11.3.1 power-on (cold) reset (por) during the rise of power supplies the v io supply voltage must remain l ess than or equal to the v cc supply voltage. v ih also must remain less than or equal to the v io supply. the cold reset embedded algorithm requires a rel atively long, h undreds of s, period (t vcs ) to load all of the eac algorithms and default state from non-volatile m emory. during the cold reset p eriod all control signals inclu ding ce# and reset# are ignored. if ce# is low during t vcs the device may draw higher than normal por current during t vcs but the level of ce# will not affect the cold reset ea. ce# or oe# must trans ition from high to low after t vcs for a valid read or write operation. reset # may be hig h or low during t vcs . if reset# is low during t vcs it may remain low at the end of t vcs to hold the devic e in the hardware reset state. if reset# is high at the end of t vcs the device will go to the standby state. when power is first applied , with supply voltage below v rst then rising to reach operating range minimum, internal device configuration and warm reset acti vities are initiated. ce# is i gnored for the duration of the por operation (t vcs or t vios ). reset# low during this por period is optional. if reset# is driven low during por it must satisfy t he hardware reset parameters t rp and t rph . in which case the reset operat ions will be completed at the l ater of t vcs or t vios or t rph . during cold reset the device will draw i cc7 current. table 11.2 power on and reset parameters parameter description limit value unit t vcs v cc setup time to first access (notes 1 , 2 ) min 300 s t vios v io setup time to first access (notes 1 , 2 ) min 300 s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 50 ns t ceh ce# pulse width high min 20 ns v io 0.0 v 0.5 v io 0.5 v io output measurement level input
document number: 001-98285 rev. *o page 77 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.3 power-up diagram 11.3.2 hardware (warm) reset during hardware reset (t rph ) the device will draw i cc5 current. when reset# continue s to be held at v ss , the device draws cmos standby current (i cc4 ). if reset# is held at v il , but not at v ss , the standby curre nt is greater. if a cold reset has not been completed by the device when reset # is asserted low after t vcs , the cold reset# ea will be performed instead of the w arm reset#, requiring t vcs time to complete. see figure 11.4, hardware reset on page 77 . after the device has completed p or and entered th e standby stat e, any later transition to the h ardware reset state will initia te the warm reset embedded algorithm. a warm reset is mu ch shorter tha n a cold reset, ta king tens of s (t rph ) to complete. during the warm reset ea, any in progr ess embedded algorithm is stoppe d and the eac is returned to its por state without reloading eac algorithms from non-volatile memory. after the warm reset e a completes, the interface will remain in the hardware reset state if reset# remain s low. when reset# retu rns high the inter face will transit to the standby state. if reset# is high at th e end of the warm rese t ea, the interface wi ll directly transit t o the standby state. if por has not been properly c ompleted by the end of t vcs , a later transition to the hardw are reset state will cause a t ransition to the power-on reset interface state and initiate the cold reset embedded algorithm. this ensures the device can complete a cold reset even if some asp ect of the system pow er-on voltage ramp-u p causes the por to not initiate or complete correctly. the ry/ by# pin is low during cold or wa rm reset as an in dication that the device is busy performing reset operations. hardware reset is initiated by the reset# signal going to v il . figure 11.4 hardware reset vcc vio reset# ce# trh tvios tvcs tceh reset# ce# trp trph trh tceh
document number: 001-98285 rev. *o page 78 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 11.4 ac characteristics 11.4.1 asynchronous read operations note: 1. not 100% tested. table 11.3 read operation v io = v cc = 2.7v to 3.6v (-40c to +85c) parameter description test setup speed option unit jedec std 90 100 110 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 90 100 ns 512 mb, 1 gb 100 110 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 90 100 ns 512 mb, 1 gb 100 110 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 90 100 ns 512 mb, 1 gb 100 110 t pacc page access time 128 mb, 256 mb max 15 20 ns 512 mb, 1 gb 15 20 t glqv t oe output enable to output delay max 25 ns t axqx t oh output hold time from ad dresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output ena ble to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s table 11.4 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v (-40c to +85c) parameter description test setup speed options unit jedec std 100 110 120 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 100 110 ns 512 mb, 1 gb 110 120 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t pacc page access time 128 mb, 256 mb max 25 30 ns 512 mb, 1 gb 25 30 t glqv t oe output enable to ou tput delay max 35 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or output enable to output high- z (note 1) max 20 ns
document number: 001-98285 rev. *o page 79 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. not 100% tested. note: 1. not 100% tested. t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s table 11.5 read operation v io = v cc = 2.7v to 3.6v (- 40c to +105c) parameter description test setup speed option unit jedec std 100 110 120 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 100 110 ns 512 mb, 1 gb 110 120 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 100 110 ns 512 mb, 1 gb 110 120 t pacc page access time 128 mb, 256 mb max 15 20 ns 512 mb, 1 gb 15 20 t glqv t oe output enable to output delay max 25 ns t axqx t oh output hold time fro m addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or outpu t enable to output high-z (note 1) max 15 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s table 11.6 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v (-40c to +105c) parameter description test setup speed option unit jedec std 110 120 130 t avav t rc read cycle time (note 1) 128 mb, 256 mb min 110 120 ns 512 mb, 1 gb 120 130 t avqv t acc address to output delay ce# = v il oe# = v il 128 mb, 256 mb max 110 120 ns 512 mb, 1 gb 120 130 t elqv t ce chip enable to output delay oe# = v il 128 mb, 256 mb max 110 120 ns 512 mb, 1 gb 120 130 table 11.4 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v (-40c to +85c) (continued) parameter description test setup speed options unit jedec std 100 110 120
document number: 001-98285 rev. *o page 80 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. not 100% tested. figure 11.5 back to back read (t acc ) operation timing diagram figure 11.6 back to back read operation (t rc )timing diagram note: back to back operations, in which ce# remains low between accesses, requires an address change to initiate the second access. t pacc page access time 128 mb, 256 mb max 25 30 ns 512 mb, 1 gb 25 30 t glqv t oe output enable to output delay max 35 ns t axqx t oh output hold time fro m addresses, ce# or oe#, whichever occurs first min 0 ns t ehqz t df chip enable or outpu t enable to output high-z (note 1) max 20 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t assb automatic sleep to standby time (note 1) ce# = v il , address stable typ 5 s max 8 s table 11.6 read operation v io = 1.65v to v cc , v cc = 2.7v to 3.6v (-40c to +105c) (continued) parameter description test setup speed option unit jedec std 110 120 130 amax-a0 ce# oe# dq15-dq0 tacc toe tce tdf tdf toh toh toh amax-a0 ce# oe# dq15-dq0 trc tacc toe tce tdf toh toh
document number: 001-98285 rev. *o page 81 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.7 page read timing diagram note: word configuration: toggle a0, a1, a2, and a3. amax-a4 a3-a0 ce# oe# dq15-dq0 tacc toe tce tpacc
document number: 001-98285 rev. *o page 82 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 11.4.2 asynchronous write operations note: 1. not 100% tested. figure 11.8 back to back write oper ation timing diagram table 11.7 write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling or following status register read. min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# pulse width min 25 ns t whwl t wph we# pulse width high min 20 ns amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs tch
document number: 001-98285 rev. *o page 83 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.9 back to back (ce#vil) wri te operation timing diagram figure 11.10 write to read (t acc ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tds tdh twp tas tah twph twc tcs amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tdf tdf toh toh toh tas tah tds tdh twp tcs tsr_w
document number: 001-98285 rev. *o page 84 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.11 write to read (t ce ) operation timing diagram figure 11.12 read to write (ce# v il ) operation timing diagram amax-a0 ce# oe# we# dq15-dq0 tacc toe toeh tce tdf tdf toh toh toh tas tah tds tdh twp tcs tch tsr_w amax-a0 ce# oe# we# dq15-dq0 tas tds tah tdh tch tacc tce toe toh toh tdf twp tghwl
document number: 001-98285 rev. *o page 85 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.13 read to write (ce# toggle) operation timing diagram notes: 1. not 100% tested. 2. upon the rising edge of we#, must wait t sr/w before switching to another address. 3. see table 5.4 on page 43 and table 5.5 on page 44 for specific values. table 11.8 erase/program operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t whwh1 t whwh1 write buffer program operation typ (note 3) s effective write buffer program operation per word typ (note 3) s program operation per word or page typ (note 3) s t whwh2 t whwh2 sector erase operation (note 1) typ (note 3) ms t busy erase/program valid to ry/by# delay max 80 ns t sr/w latency between read an d write operations (note 2) min 10 ns t esl erase suspend latency max (note 3) s t psl program suspend latency max (note 3) s t rb ry/by# recovery time min 0 s amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tas tcs tds tah tdh twp tch toh toh toh tdf tdf tghwl
document number: 001-98285 rev. *o page 86 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.14 program operation timing diagram note: 1. pa = program address, pd = program data, d out is the true data at the program address. figure 11.15 chip/sector erase op eration timing diagram note: 1. sa = sector address (for sector erase), va = valid address for reading status data. oe# we# ce# data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa oe# ce# addresses we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase t ds t cs t dh t ch t whwh2 va va erase command sequence (last two cycles) read status data (last two cycles) ry/by# t rb t busy 30h in progress complete 55h
document number: 001-98285 rev. *o page 87 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. if this timing cannot be achieved, perform the following steps immediately after aso exit and before resuming normal processi ng: read one word from each of 64 unique 32 byte-aligned pages. figure 11.16 aso entry timing note: 1. applicable to any aso entry command. figure 11.17 data# polling timing diagram ( during embedded algorithms) note: 1. va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read cycle. table 11.9 aso entry timing t asostart falling edge of ce# or addre ss change whichever comes last t asoend rising edge of ce# or rising ed ge of we# whichever comes first t asoentry 25 ns < t asoentry < 50 ns or t asoentry > 150 ns ce# we# addresses first command cycle to enter aso t asostart t asoend t asoentry we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement valid data valid data t acc t rc status data tr u e
document number: 001-98285 rev. *o page 88 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s figure 11.18 toggle bit timing diagram (during embedded algorithms) note: 1. dq6 will toggle at any read address while the device is busy. dq 2 will toggle if the address is within the actively erasing s ector. figure 11.19 dq2 vs. dq6 relationship diagram note: 1. the system may use oe# or ce# to toggle dq2 and dq6. dq2 toggles only when read at an address within the erase-suspended sect or. 11.4.3 alternate ce# cont rolled write operations table 11.10 alternate ce# controlled write operations parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t aso address setup time to oe # low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t 0eph oe# high during toggle bit polling min 20 ns oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
document number: 001-98285 rev. *o page 89 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s note: 1. not 100% tested. figure 11.20 back to back (ce#) write operation timing diagram figure 11.21 (ce#) write to read o peration timing diagram t ghek t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t elwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 20 ns table 11.10 alternate ce# controlled write operations (continued) parameter description v io = 2.7v to v cc v io = 1.65v to v cc unit jedec std amax-a0 ce# oe# we# dq15-dq0 tds tdh tas tah twc tcp tcph tws twh amax-a0 ce# oe# we# dq15-dq0 tacc toe tce tdf toh twc tas tah tds tdh tws twh toeh
document number: 001-98285 rev. *o page 90 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12. physical interface 12.1 56-pin tsop 12.1.1 connection diagram figure 12.1 56-pin standard tsop notes: 1. pin 28, do not use (dnu), a device internal signal is connected to the package connec tor. the connector may be used by cypres s for test or other purposes and is not intended for connection to any host system signal. do not us e these connections for pcb sign al routing channels. though not recommended, the ball can be connected to v cc or v ss through a series resistor. 2. pin 27, 30, and 53 reserved for future use (rfu). 3 18 4 1 2 5 6 7 8 9 10 19 20 21 22 23 24 11 12 13 14 15 16 17 46 45 48 47 44 43 42 40 41 54 53 55 56 52 51 50 49 39 38 37 36 35 34 33 32 31 30 56-pin tsop 25 26 27 28 29 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp# ry/by# a17 a7 a6 a5 a23 a22 a4 a3 a2 a1 rfu dnu a24 a25 dq10 a16 rfu v ss dq15 dq7 dq14 dq6 dq2 dq9 dq1 dq8 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq0 oe# v ss ce# a0 v io rfu nc for gl256s, gl128s nc for gl512s, gl256s, gl128s nc for gl128s
document number: 001-98285 rev. *o page 91 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.1.2 physical diagram figure 12.2 56-pin thin small outline package (tsop) , 14 x 20 mm notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
document number: 001-98285 rev. *o page 92 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.2 64-ball fbga 12.2.1 connection diagram figure 12.3 64-ball fortified ball grid array notes: 1. ball e1, do not use (dnu), a device internal signal is connec ted to the package connector. the connector may be used by cypre ss for test or other purposes and is not intended for connection to any host system signal. do not us e these connections for pcb sign al routing channels. though not recommended, the ball can be connected to v cc or v ss through a series resistor. 2. balls f7 and g1, reserved for future use (rfu). 3. balls a1, a8, c1, d1, h1, and h8, no connect (nc). abcd efgh 8 nc a2 2 a23 vio vss a2 4 a25 nc 7 a1 3 a12 a1 4 a15 a1 6 rfu dq15 vss 6 a9 a8 a1 0 a11 dq7 dq14 dq13 dq6 5 we# reset# a21 a19 dq5 dq12 vcc dq4 4 ry/by# wp# a18 a20 dq2 dq10 dq11 dq3 3 a7 a1 7 a6 a5 dq0 dq8 dq9 dq1 2 a3 a4 a2 a1 a0 ce# oe# vss 1 nc dnu vio rfu nc top view product pinout - nc for gl128s nc for gl512s, gl256s, gl128s nc for gl256s, gl128s nc nc nc
document number: 001-98285 rev. *o page 93 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.2.2 physical diagram C lae064 figure 12.4 lae06464-ball fortified ball grid array (fbga), 9 x 9 mm package lae 064 jedec n/a 9.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 9.00 bsc. body size e 9.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement ? none depopulated solder balls 3623 \ 16-038.12 \ 1.16.0 7 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010? except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in ? the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls.
document number: 001-98285 rev. *o page 94 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.2.3 physical diagram C laa064 3354 \ 16-038.12d package laa 064 jedec n/a 13.00 mm x 11.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement none depopulated solder balls notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls.
document number: 001-98285 rev. *o page 95 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.3 56-ball fbga 12.3.1 connection diagram figure 12.5 56-ball fortified ball grid array notes: 1. ball g1, do not use (dnu), a device internal signal is connecte d to the package connector. the connector may be used by cypre ss ? for test or other purposes and is not intended for connection to any host system signal. do not us e these connections for pcb sign al routing channels. though not recommended, the ball can be connected to v cc or v ss through a series resistor. 2. balls e7, f8, and h5, reserved for future use (rfu). 3. balls a3 and b3, no connect (nc). 8 7 6 5 4 3 2 1 top view product pinout 512 mb & 256 mb only a21 a15 a16 a22 vss rfu/a24 a13 a12 rfu a14 dq7 dq15 dq14 a11 a9 a19 dq6 a10 dq12 dq13 dq5 a8 a20 rfu/a23 vio dq4 rfu we# ry/by# reset# vcc dq3 dq11 wp# a18 nc dq1 a17 dq10 dq9 dq2 nc a5 a6 vss a4 dq0 oe# dq8 a7 a2 a3 a0 a1 dnu ce# abcd efg h supports wp# only, not wp#/acc 512 mb only
document number: 001-98285 rev. *o page 96 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 12.3.2 physical diagram - vbu 056 13. special handling instru ctions for fbga package special handling is required for flash memory pro ducts in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning meth ods. the package and/or data integrity may be compr omised if the package body is exposed to temperatures above 150c for prolonged periods of time. seating plane e1 7 se d1 e a c db e f g h 7 8 6 5 3 2 1 e 4 a1 corner 7 sd bottom view c c a d e c 0.10 (2x) c 0.10 b (2x) c 9 side view top view index mark a1 a a1 corner 0.10 0.08 b a c m m c 0.08 0.15 6 56 b g1055\ 16-038.25 \ 01.26.12 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the total number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10. outline and dimensions per customer requirement. package vbu 056 jedec n/a 9.00 mm x 7.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.17 --- --- ball height d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. ball footprint e1 5.60 bsc. ball footprint md 8 row matrix size d direction me 8 row matrix size e direction n 56 total ball count b 0.35 0.40 0.45 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls
document number: 001-98285 rev. *o page 97 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 14. ordering information valid combinations standard table 14.1 lists configurations planned to be available in volume. the ta ble will be updated as new combinations are released. consult your local sales representative to confirm availability of specific combinations and to check on newly released combin ations. table 14.1 s29gl-s valid combi nations standard s29gl-s valid combin ations standard base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type) s29gl01gs 100 dhi, fai, fhi, tfi (note 1) 01, 02 0, 3 (note 2) s29gl01gs10dhiyyx s29gl01gs10faiyyx s29gl01gs10fhiyyx s29gl01gs10tfiyyx 110 dhv, tfv (note 1) 01, 02 s29gl01gs11dhvyyx s29gl01gs11tfvyyx dhi, fhi, tfi (note 1) v1, v2 s29gl01gs11dhiyyx s29gl01gs11fhiyyx s29gl01gs11tfiyyx 120 dhv, tfv (note 1) v1, v2 s29gl01gs12dhvyyxx s29gl01gs12tfvyyxx s29gl512s 100 dhi, fai, fhi, ghi, sfi, tfi (note 1) 01, 02 0, 3 (note 2) s29gl512s10dhiyyx s29gl512s10faiyyx s29gl512s10fhiyyx s29gl512s10ghiyyx s29gl512s10sfiyyx s29gl512s10tfiyyx 110 ghi (note 1) 01, 02 s29gl512s11ghiyyx dhv, tfv (note 1) 01, 02 s29gl512s11dhvyyx s29gl512s11tfvyyx dhi, fhi, tfi (note 1) v1, v2 s29gl512s11dhiyyx s29gl512s11fhiyyx s29gl512s11tfiyyx 120 dhv, tfv (note 1) v1, v2 s29gl512s12dhvyyxx s29gl512s12tfvyyxx S29GL256S 90 dhi, fhi, ghi, tfi (note 1) 01, 02 0, 3 (note 2) S29GL256S90dhiyyx S29GL256S90fhiyyx S29GL256S90ghiyyx S29GL256S90tfiyyx 100 dhv, tfv (note 1) 01, 02 S29GL256S10dhvyyx S29GL256S10tfvyyx dhi, fai, fhi, tfi (note 1) v1, v2 S29GL256S10dhiyyx S29GL256S10faiyyx S29GL256S10fhiyyx S29GL256S10tfiyyx 110 dhv, tfv (note 1) v1, v2 S29GL256S11dhvyyxx S29GL256S11tfvyyxx
document number: 001-98285 rev. *o page 98 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s notes: 1. additional speed, package, and temperature options maybe offe red in the future. check with your local sales representative fo r availability. 2. package type 0 is standard option. s29gl128s 90 dhi, fai, fhi, ghi, tfi (note 1) 01, 02 0, 3 (note 2) s29gl128s90dhiyyx s29gl128s90faiyyx s29gl128s90fhiyyx s29gl128s90ghiyyx s29gl128s90tfiyyx 100 dhv, tfv (note 1) 01, 02 s29gl128s10dhvyyx s29gl128s10tfvyyx dhi, fai, fhi, tfi (note 1) v1, v2 s29gl128s10dhiyyx s29gl128s10faiyyx s29gl128s10fhiyyx s29gl128s10tfiyyx 110 dhv, tfv (note 1) v1, v2 s29gl128s11dhvyyxx s29gl128s11tfvyyxx table 14.1 s29gl-s valid combinations standard (continued) s29gl-s valid combin ations standard base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type)
document number: 001-98285 rev. *o page 99 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s valid combinations aut omotive grade / aec-q100 table 14.2 and table 14.3 list configurations that are automotive grade / aec-q100 quali fied and are planned to be available in volume. the table will be updated a s new combinations are relea sed. consult your local sales repr esentative to confirm availab ility of specific combinations and to ch eck on newly released combina tions. production part approval process (ppap) support is only provide d for aec-q100 grade products. products to be used in end-use applications that require iso/ts -16949 compliance must be aec-q100 grade products in combination with ppap. nonCaec-q 100 grade products are not manu factured or documented i n full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap support f or end-use applications that do not require iso/ts-16949 compliance. notes: 1. additional speed, package, and temperature options maybe offe red in the future. check with your local sales representative fo r availability. 2. package type 0 is standard option. table 14.2 s29gl-s valid combinations aut omotive grade (-40c to +85c) s29gl-s valid combinations auto motive grade (-40c to +85c) base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type) s29gl01gs 100, 110 dha, fha, tfa (note 1) 01, 02 0, 3 (note 2) s29gl01gs10dhayyx s29gl01gs10fhayyx s29gl01gs10tfayyx s29gl01gs11dhayyx s29gl01gs11fhayyx s29gl01gs11tfayyx 110 v1, v2 s29gl01gs11dhayyx s29gl01gs11fhayyx s29gl01gs11tfayyx s29gl512s 100 01, 02 s29gl512s10dhayyx s29gl512s10fhayyx s29gl512s10tfayyx 110 v1, v2 s29gl512s11dhayyx s29gl512s11fhayyx s29gl512s11tfayyx S29GL256S 90 01, 02 S29GL256S90dhayyx S29GL256S90fhayyx S29GL256S90tfayyx 100 v1, v2 S29GL256S10dhayyx S29GL256S10fhayyx S29GL256S10tfayyx s29gl128s 90 01, 02 s29gl128s90dhayyx s29gl128s90fhayyx s29gl128s90tfayyx 100 v1, v2 s29gl128s10dhayyx s29gl128s10fhayyx s29gl128s10tfayyx
document number: 001-98285 rev. *o page 100 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s notes: 1. additional speed, package, and temperature options maybe offe red in the future. check with your local sales representative fo r availability. 2. package type 0 is standard option. table 14.3 s29gl-s valid combinations aut omotive grade (-40c to +105c) s29gl-s valid combinations aut omotive grade (-40c to +105c) base opn speed (ns) package and temperature model number packing type ordering part number (yy = model number, x = packing type) s29gl01gs 110 dhb, fhb, tfb (note 1) 01, 02 0, 3 (note 2) s29gl01gs11dhbyyx s29gl01gs11fhbyyx s29gl01gs11tfbyyx 120 v1, v2 s29gl01gs12dhbyyx s29gl01gs12fhbyyx s29gl01gs12tfbyyx s29gl512s 110 01, 02 s29gl512s11dhbyyx s29gl512s11fhbyyx s29gl512s11ghbyyx s29gl512s11tfbyyx 120 v1, v2 s29gl512s12dhbyyx s29gl512s12fhbyyx s29gl512s12ghbyyx s29gl512s12tfbyyx S29GL256S 100 01, 02 S29GL256S10dhbyyx S29GL256S10fhbyyx S29GL256S10tfbyyx 110 v1, v2 S29GL256S11dhbyyx S29GL256S11fhbyyx S29GL256S11tfbyyx s29gl128s 100 01, 02 s29gl128s10dhbyyx s29gl128s10fhbyyx s29gl128s10tfbyyx 110 v1, v2 s29gl128s11dhbyyx s29gl128s11fhbyyx s29gl128s11tfbyyx
document number: 001-98285 rev. *o page 101 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s the ordering part number for the general market device is forme d by a valid combination of the following: s29gl01gs 10 d h i 01 0 packing type 0 = tray 3 = 13 tape and reel model number (v io and v cc range) 01 = v io = v cc = 2.7 to 3.6v, highest address sector protected 02 = v io = v cc = 2.7 to 3.6v, lowest address sector protected v1 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, highest address sector protected v2 = v io = 1.65 to v cc , v cc = 2.7 to 3.6v, lowest address sector protected temperature range / grade i = industrial (-40 c to +85 c) v = industrial plus (-40 c to +105 c) a = automotive, aec-q100 grade 3 (-40 c to +85 c) b = automotive, aec-q100 grade 2 (-40 c to +105 c) package materials set a = leaded (sn/pb) balls - bga only f = lead free (pb-free) h = low halogen, pb-free package type d = fortified ball-grid array package (lae064) 9 mm x 9 mm f = fortified ball-grid array package (laa064) 13 mm x 11 mm g = fortified ball-grid array package (vbu056) 9 mm x 7 mm s = 70-pin shrink small outline package t = thin small outline package (tsop) standard pinout speed option 90 = 90 ns random access time 10 = 100 ns random access time 11 = 110 ns random access time 12 = 120 ns random access time device number/description s29gl01gs, s29gl512s, S29GL256S, s29gl128s 3.0 volt core, with v io option, 1024, 512, 256, 128 megabit page-mode flash memory, manufactured on 65 nm mirrorbit eclipse process technology
document number: 001-98285 rev. *o page 102 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 15. other resources 15.1 cypress flash memory roadmap http://www.cypress. com/flash-roadmap 15.2 links to software http://www.cypress.com/ software-and-drivers -cypress-flash-memor y 15.3 links to application notes http://www.cypress.com/cypressappnotes
document number: 001-98285 rev. *o page 103 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s 16. revision history document history page document title: s29gl01gs/s29gl5 12s/S29GL256S/s 29gl128s, 1-gbit (128 mbyte)/512-mbit (64 mbyte)/256-mbit (32 mbyte)/128-mbit (16 mbyte) , 3.0 v, gl-s flash memory document number: 001-98285 rev. ecn no. orig. of change submission date description of change ** ? bwha 02/11/2011 initial release. *a ? bwha 03/21/2011 global: modified document from ad vance informatio n to prelim inary opn: added fbga package offering for v1 & v2 model number removed kgd information, which is documented in a separate supp lement command definitions table: removed duplicated commands changed the nu mber of command cycles for a cfi enter from 3 to 1 physical interface: updated 56-pin tsop pinout figure updated 64-ball fbga pinout figure other resources: added additional application notes in links t o application notes lock register table: changed the default value of bit 7 in the lock register *b ? bwha 07/08/2011 performance summary: updated tabl e: typical program and erase r ates secure silicon region aso: correct ed table: secure silicon regi on dq1: write-to-buffer abort: co rrected table: data polling staus embedded algorithm performance ta ble: updated table: embedded a lgorithm characteristics command state transitions: corrected tables: changed software reset/aso exit data value to from 00f0h to xf0h corrected table: erase suspend un lock state command transition corrected table: erase suspend - dyb state command transition corrected table: program unlo ck state command transition corrected table: lock regist er state command transition corrected table: secure silicon sector program state command tr ansition corrected table: password protec tion command state transition corrected table: non-volatile pro tection command state transiti on corrected table: ppb lock bit command state transition corrected table: volatile sector protection command state trans ition
document number: 001-98285 rev. *o page 104 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s b (cont) ? bwha 07/08/2011 device id and common flash i nterface (id-cfi) aso map: corrected table: corrected cfi pr imary vendor-specific extended query de- scription for word address (sa) + 0045h dc characteristics: updated vil max updated note power-on reset (por) and warm reset: updated table: added row t o bottom of table power-on (cold) reset (por): updated text updated figure: power-up diagram hardware (warm) reset: updat ed figure: hardware reset asynchronous write operations: added figure: back to back (ce#vi l) write operation timing diag ram updated table: erase/program operations physical diagram - laa064: added figure *c ? bwha 10/03/2011 power-up write inhibit: minor correction ppb password protection m ode: minor correction embedded algorithm characteristi cs table: updated buffer progra mming time maximum limits absolute maximum ratings table: added clarification dc characteristics table: outpu t high voltage clarification power-up/power-down voltage and timing table: added clarificati on power-up figure: added clarification power-on (cold) reset (por): added clarification valid combinations table: updated table *d ? bwha 12/14/2011 global: data sheet designation changed fr om preliminary to full product ion sector erase: updated typical erase time capacitance characteristics: updated section ordering information: corrected note designation in valid combi nation table *e ? bwha 03/16/2012 global: added 9 mm x 7 mm package added 105c offering ordering information: updated valid combinations document history page (continued) document title: s29gl01gs/s29gl5 12s/S29GL256S/s 29gl128s, 1-gbit (128 mbyte)/512-mbit (64 mbyte)/256-mbit (32 mbyte)/128-mbit (16 mbyte) , 3.0 v, gl-s flash memory document number: 001-98285 rev. ecn no. orig. of change submission date description of change
document number: 001-98285 rev. *o page 105 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s f ? bwha 12/21/2012 distinctive characteristics: added in-cabin temperature range status register aso: added clarification advanced sector protection overview: updated figure ppb lock: added clarification persistent protection bits (ppb): added clarification dynamic protection bits (dyb): added clarification ppb password protection mode: added clarification chip erase: added clarification sector erase: adde d clarification erase suspend / erase re sume: added clarification status register aso: added clarification status registeradded clarification dq7: data# polling: added clarification dq1: write-to-buffer abort: added clarification data polling status: updated table embedded operation erro r: added clarification protection error: a dded clarification write buffer abort: added clarification performance table: updated embedded algorithm characteristics ( -40c to +105c) table device id and common flash i nterface (id-cfi) aso map: updated cfi device geom etry definition table updated cfi primary vendor-spe cific extended query table asynchronous read operations: ad ded read operation vio = 1.65 ( -40c to +105c) table asynchronous write operations: updated read to write (ce# vil) figure updated read to write (ce# toggle) figure *g ? bwha 10/09/2015 s29gl-s valid combinations table : added vio models for automoti ve in cabin temperature range *h 4871480 bwha 08/13/2015 u pdated to new template. *i 5162387 rysu 03/04/2016 updated ordering information on page 97 : updated part numbers. replaced in cabin with indust rial plus in ordering code def initions below table 14.1 on page 97 . updated to new template. *j 5428780 bwha 09/06/2016 updated timing specifications on page 75 : updated ac characteristics on page 78 : updated asynchronous write operations on page 82 : updated table 11.9 on page 87 . updated figure 11.16 on page 87 . document history page (continued) document title: s29gl01gs/s29gl5 12s/S29GL256S/s 29gl128s, 1-gbit (128 mbyte)/512-mbit (64 mbyte)/256-mbit (32 mbyte)/128-mbit (16 mbyte) , 3.0 v, gl-s flash memory document number: 001-98285 rev. ecn no. orig. of change submission date description of change
document number: 001-98285 rev. *o page 106 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s k 5446870 bwha 11/10/2016 added automotive grade related information in all instances acr oss the docu- ment. updated address space maps on page 6 : added ecc status aso on page 11 . updated embedded operations on page 20 : added automatic ecc on page 22 . updated command set on page 23 : added ecc status aso on page 33 . updated data integrity on page 54 : added erase endurance on page 54 . added data retention on page 54 . updated software interface reference on page 55 : removed address and data configuration. updated command summary on page 55 : updated table7.1 onpage55 (to include ecc aso commands). updated electrical specifications on page 69 : added thermal resistance on page 69 . updated ordering information on page 97 : added valid combinations automotiv e grade / aec-q100 on page 99 . updated other resources on page 102 : added cypress flash memory roadmap on page 102 . updated links to software on page 102 : updated description. updated links to application notes on page 102 : updated description. removed specification bulletins. removed contacting cypress. l 5724042 nfb / prit 05/03/2017 updated software interface reference on page 55 : added device id and common flash interface (id-cfi) aso map on page 63 . updated ordering information on page 97 : updated valid combinations standard on page 97 : updated table 14.1 on page 97 (to include s29gl512s10sfi020). updated to new template. m 5776117 sx 06/16/2017 updated software interface reference on page 55 : updated command summary on page 55 : updated table7.1 onpage55 : replaced 2 with 1 in cycles column corresponding to comm and set exit under ecc aso command sequence. document history page (continued) document title: s29gl01gs/s29gl5 12s/S29GL256S/s 29gl128s, 1-gbit (128 mbyte)/512-mbit (64 mbyte)/256-mbit (32 mbyte)/128-mbit (16 mbyte) , 3.0 v, gl-s flash memory document number: 001-98285 rev. ecn no. orig. of change submission date description of change
document number: 001-98285 rev. *o page 107 of 108 s29gl01gs/s29gl512s S29GL256S/s29gl128s n 5827786 prit 07/21/2017 updated address space maps on page 6 : updated ecc status aso on page 11 : updated description. updated ecc status on page 11 : updated description. updated table 2.8 on page 12 (updated name corresponding to bit 2 and bit 1). updated embedded operations on page 20 : updated command set on page 23 : updated aso entry and exit on page 31 : updated ecc status aso on page 33 : updated description. completing sunset review. o 5891084 prit 09/19/2017 updated ordering information on page 97 : updated valid combinations standard on page 97 : updated table 14.1 on page 97 (to include s29gl01gs10faiyyx, s29gl512s10faiyyx, s29 gl256s10faiyyx, s29gl 128s90faiyyx and s29gl128s10faiyyx). document history page (continued) document title: s29gl01gs/s29gl5 12s/S29GL256S/s 29gl128s, 1-gbit (128 mbyte)/512-mbit (64 mbyte)/256-mbit (32 mbyte)/128-mbit (16 mbyte) , 3.0 v, gl-s flash memory document number: 001-98285 rev. ecn no. orig. of change submission date description of change
document number: 001-98285 rev. * o revised september 21, 2017 pa ge 108 of 108 ? cypress semiconductor corporation, 2011C2017. this document i s the property of cypress semiconductor corporation and its sub sidiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in th is document ("software"), is owned by cypress under the intelle ctual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and tre aties and does not, except as specifically stated in this parag raph, grant any license under its patents, copyrights, trademar ks, or other intellectual property rights. if the software is not accompani ed by a license agreement and you do not otherwise have a writt en agreement with cypress governing the use of the software, th en cypress hereby grants you a personal, non-exclusive, nontransferable li cense (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source cod e form, to modify and reproduce the software solely for use with cypress h ardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributo rs), solely for use on cypress hardware product units, and (2) under those claims of cypress's patents that are infringed by t he software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware produc ts. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no war ranty of any kind, express or im plied, with regard to this docu ment or any software or accompanying hardware, includi ng, but not limited to, the im plied warranties of merchantability and fitness for a particula r purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informa tion or programming code, is provided only for reference purpos es. it is the responsibility of the user of this document to properly des ign, program, and test the functionality and safety of any appl ication made of this information and any resulting product. cy press products are not designed, intended, or authorized for use as critical c omponents in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support d evices or systems, other medical devices or systems (including resuscitat ion equipment and surgical implants), pollution control or haza rdous substances management, or other uses where the failure of the device or system could cause personal injury, death, or propert y damage ("unintended uses"). a critical component is any compo nent of a device or system whose failure to perform can be reas onably expected to cause the failure of the device or system, or to af fect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unint ended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims fo r personal injury or death, ari sing from or related to any unint ended uses of cypress products . cypress, the cypress logo, spansion, the spansion logo, and com binations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tr aveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and bran ds may be claimed as property of their respective owners. s29gl01gs/s29gl512s S29GL256S/s29gl128s sales, solutions, an d legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers representati ves, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of S29GL256S

	To Download S29GL256S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .